Low-Power Brain-Machine Interfaces

Recent pioneering work on monkeys and humans by several neurobiologists around the world has resulted in brain-machine interfaces that promise a cure for patients who are paralyzed: Such interfaces use electrodes to record from neurons in motor regions of the brain, decode the intention of the subject to move, and use this decoded signal to move a robotic limb or a computer cursor. Such interfaces require neural recording and amplification from 10 to 100 electrodes, digitization and decoding of these signals to extract the intention to move, wireless telemetry of information from implanted circuitry within the brain to circuitry outside the brain, wireless telemetry of programming parameters from outside the brain to implanted circuitry within the brain, and wireless recharging of implanted circuitry for power.

Work in our lab focuses on building ultra-low-power and miniature circuitry for brain-machine interfaces which could enable them to work on an implanted 100mAh battery for 10 years or more and minimize heat dissipation in the brain. Current interfaces are bulky, 100-10,000 times more power hungry, and often lack wireless capabilities. As part of these ongoing efforts, we have just built the world's most energy-efficient and low-power neural amplifier, developed very efficient wireless recharging links, and successfully stimulated the brain of a zebra finch bird wirelessly. We are researching the development of ultra-low-power analog decoding algorithms for compression, decoding, and learning, ultra-low-power circuits for spike sorting, recognition, and decoding, adaptive strategies for neural amplification to further lower power, and ultra-low-power wireless telemetry circuits. We are also researching strategies for decoding and recording that will enable longevity of implanted electrodes in the brain.Our work promises to enable large-scale, chronic experimental neuroscience systems (100 to 10,000 electrodes or more). It is useful in prosthetics for paralysis, for the blind, for Parkinson's disease, and for epilepsy. Brain-machine interfaces are important for several future applications as well in other sensing, motor, or cognitive modalities. Our work is being done in collaboration with neurobiologists and engineers including Professor Richard Andersen's group at CalTech (work on paralysis), Professor Michale Fee's group at MIT (work on experimental neuroscience), and with Professor John Wyatt's group at MIT (work on the blind).

Selected Publications

1. ENERGY-EFFICIENT NEURAL RECORDING AMPLIFIER: W. Wattanapanitch, M. Fee and R. Sarpeshkar, "An Energy-Efficient Micropower Neural Recording Amplifier", IEEE Transactions on Biomedical Circuits and Systems, vol. 1, No. 2, pp. 136-147, June 2007.

2. LOW-POWER BRAIN-MACHINE CIRCUITS: R. Sarpeshkar, W. Wattanapanitch, B. Rapoport, S. K. Arfin, M. W. Baker, S. Mandal, M. Fee, S. Musallam, and R. Andersen, "Low-Power Circuits for Brain-Machine Interfaces", Proceedings of the IEEE Symposium on Circuits and Systems, pp. 2068-2071, May 2007.

3. RF WIRELESS RECHARGING:M.W. Baker and R. Sarpeshkar, “Feedback Analysis and Design of RF Power Links for Low-Power Bionic Systems,” IEEE Transactions of Biomedical Circuits and Systems, Vol. 1, No. 1, pp. 28—38, April 2007.

4. BLOCKING-CAPACITOR-FREE ELECTRODE STIMULATION: J. Sit and R. Sarpeshkar, "A low-power, blocking-capacitor-free, charge-balanced electrode-stimulator chip with less than 6nA DC error for 1mA full-scale stimulation," IEEE Transactions on Biomedical Circuits and Systems,  Vol. 1, No. 3,  pp. 172-183, September 2007.

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Bionic Ear

This project focuses on the design of ultra-low-power cochlear-implant systems for the deaf, research that could enable fully implanted systems to become a reality. A recent success from the lab resulted in an analog bionic ear processor that cut power consumption by more than an order of magnitude over the best A-D-then-DSP digital solutions. The power consumption of this processor is so low that it will enable 30 year operation on a 100mAh rechargeable battery. Although this chip is an analog chip, it has 86 programmable subject parameters and is robust to power-supply noise, thermal noise, 1/f noise, transistor mismatch, and temperature variations. The chip is being explored for use in portable speech recognition systems as well.

Work in the lab has led to a bio-inspired asynchronous interleaved sampling algorithm (AIS) and chip for low-power processing and neural stimulation. The AIS algorithm encodes phase information with good fidelity, an important requirement for music.

The silicon cochlea maps the biophysics of the inner ear to a chip. The silicon cochlea has the potential to revolutionize speech recognition and cochlear-implant subject performance in the presence of background noise -- a critical limiting factor today – while doing hundreds of mega floating point operations per second on a modest mW of power. A novel ear-inspired companding algorithm that arose out of work on the silicon cochlea has shown promise for improving recognition in noise in cochlear-implant subjects.

Selected Publications

1. THE ANALOG BIONIC EAR PROCESSOR (JOURNAL ARTICLE): R. Sarpeshkar, C. Salthouse, J.J. Sit, M. Baker, S. Zhak, T. Lu, L. Turicchia, and S. Balster,  “An Ultra-Low-Power Programmable Analog Bionic Ear Processor,” IEEE Transactions on Biomedical Engineering, Vol. 52, No. 4, pp. 711-727, April 2005.

2. THE ANALOG BIONIC EAR PROCESSOR (BEST PERFORMANCE):R. Sarpeshkar, M. Baker, C. Salthouse, J.J. Sit, L. Turicchia, and S. Zhak, “An Analog Bionic Ear Processor with Zero-Crossing Detection,” Proceedings of the IEEE International Solid State Circuits Conference (ISSCC), San Francisco, CA, Paper 4.2, pp. 78-79, February 6-10, 2005.

3. THE COMPANDING ALGORITHM: L. Turicchia and R. Sarpeshkar, “A Bio-Inspired Companding Strategy for Spectral Enhancement,” IEEE Transactions on Speech and Audio Processing, Vol. 13, No. 2, pp. 243-253, March 2005.

4. THE AIS ALGORITHM: J. Sit, A. M. Simonson, A. J. Oxenham, M. A. Faltys, and R. Sarpeshkar, “A low-power asynchronous interleaved sampling algorithm for cochlear implants that encodes envelope and phase information”, IEEE Transactions on Biomedical Engineering, Vol. 54, pp. 138-149, 2007.

5. THE AIS BIONIC EAR PROCESSOR: J. Sit and R. Sarpeshkar, “A Cochlear-Implant Processor for Encoding Music and Lowering Stimulation Power,” IEEE Pervasive Computing--special issue on implantable electronics, Vol. 1, No. 7, pp. 40-48, 2008.

6. THE SILICON COCHLEA: R. Sarpeshkar, R.F. Lyon, and C.A. Mead, “A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea,” Analog Integrated Circuits and Signal Processing, Vol. 13, pp. 123-151, 1997.

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Circuits for Biomedical and Other Applications

Several circuits in our lab developed for biomedical applications have uses in other domains and advance frontiers in ultra-low-power, precision, or feedback-circuit design. For example, an energy-harvesting RF-ID tag that can rectify RF energy at levels as low as 6uW, can be used for battery-free heart monitoring of electrocardiogram signals or in general-purpose RF-ID tags to create a battery. Several circuits developed for use in the bionic ear processor, e.g., low-power microphone front ends, automatic gain control circuits, filtering circuits, energy-extraction circuits, and logarithmic analog-to-digital converters, are useful in other application domains. A predictive comparator with adaptive control, developed in our lab, has been used in Professor Wyatt's lab for improving the energy efficiency of an RF power system for the blind and has applications in power-electronic systems. An ultra-low-noise capacitance-measuring circuit, capable of detecting a 1 part per 8 million change in capacitance of a MEMS capacitance sensor, is being explored for use in various bio-molecular sensing applications. Our lab has developed an analog memory element with an ultra-low-leakage switch that achieves 5 electrons per second leakage in 0.5um technology and is capable of storing an 8-bit number without degradation for over 4 hours. Some of Professor Sarpeshkar's early work at Bell Labs was important in helping pioneer the integration of organic circuits. His wide-linear-range transconductance amplifier innovated novel techniques in the use of the well of the transistor as an input, led to the invention of gate degeneration, and is widely used. He also made the first experimental measurements of noise in subthreshold transistors, which was important in revealing the deep connection between thermal noise and shot noise.

Selected Publications

1. M. Tavakoli and R. Sarpeshkar, “An Offset-Cancelling Low-Noise Lock-in Architecture for Capacitive Sensing,”  IEEE Journal of Solid State Circuits, Vol. 38, No. 2,  pp. 244-253, 2003.

2. S. Mandal and R. Sarpeshkar, “Low Power CMOS Rectifier Design for RFID Applications,” IEEE Transactions on Circuits and Systems I, Vol. 54, No. 6, June 2007.

3. A. MeVay and R. Sarpeshkar, “Predictive Comparators with Adaptive Control,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 50, No. 10 pp. 579-588, 2003.

4. M. Baker and R. Sarpeshkar, “A Low-Power High-PSRR Current Mode Microphone Preamplifier,” IEEE Journal of Solid State Circuits, Vol. 38, No. 10 pp. 1671-1678, 2003.

5. M. Baker and R. Sarpeshkar, “Low-Power Single Loop and Dual-Loop AGCs for Bionic Ears,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 9, pp 1983—1996, September 2006.

6. C. Salthouse and R. Sarpeshkar, “A Practical Micropower Programmable Bandpass Filter for use in Bionic Ears,” IEEE Journal of Solid State Circuits, Vol. 38, No. 1, pp. 63-70, 2003.

7. S. Zhak, M. Baker, and R. Sarpeshkar, “A Low Power Wide Dynamic Range Envelope Detector,” IEEE Journal of Solid State Circuits, vol. 38 (10), pp.1750-1753, 2003.

8. J.J. Sit and R. Sarpeshkar, “A micropower logarithmic A/D with offset and temperature compensation,” IEEE Journal of Solid State Circuits, Vol. 39, No. 2, pp. 308-319, 2004.

9. M. O'Halloran and R. Sarpeshkar, "A 10nW 12-bit Accurate Analog Storage Cell with 10aA Leakage,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, pp. 1985-1996 November 2004.

10. M. O'Halloran and R. Sarpeshkar, “An Analog Storage Cell with 5 electron/sec Leakage,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006), Kos, Greece, pp. 557-560, May 21-24, 2006.

11. B. Kim , S. Mandal, and R. Sarpeshkar, “Power-adaptive Operational Amplifier with Positive-Feedback Self Biasing,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006, Kos, Greece, 4 pages, May 21-24, 2006.

12. B. Crone , A. Dodabalapur, Y. Y. Lin, R. W. Filas, Z. Bao, A. LaDuca, R. Sarpeshkar, H. E. Katz, and W. Li, “Large Scale Complementary Integrated Circuits Based on Organic Transistors,” NATURE, Vol. 403, pp. 521-523, 3rd February 2000.

13. R. Sarpeshkar, R.F. Lyon, and C.A. Mead, “A Low-Power Wide-Linear-Range Transconductance Amplifier,” Analog Integrated Circuits and Signal Processing, Vol. 13, pp. 123-151, 1997.

14. R. Sarpeshkar , T. Delbruck, and C.A. Mead, “White Noise in MOS Transistors and Resistors,” IEEE Circuits and Devices, Vol. 9, No. 6, pp. 23-29, 1993.

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