Reliability Driven Optimisation: when Boole meets Shannon”
Faculty Advisor: Muriel Medard
Mentor(s): Emanuel Popovici (Engineering, University College Cork);
Contact e-mail: firstname.lastname@example.org, email@example.com
Research Area(s): Design for reliability, Boolean Networks, Error control coding, Boolean Network Coding, Decoding using faulty decoders.
Traditional logic synthesis methodologies are driven by timing, area or power consumption constraints. However, due to aggressive technology shrinking and lower power requirements, circuit reliability is fast turning out to be yet another major constraint in the VLSI design flow. Soft errors, which traditionally affected only the memories, are now also resulting in logic circuit reliability degradation. The classical optimisation techniques are making in fact the circuit more error prone by reducing the redundancy. Current techniques for reliability improvement are based on local transformations and combinatorial optimisation techniques. In this project we propose a systematic and integrated methodology to address and improve the Boolean Network reliability that are fundamentally rooted in Shannon’s theory.
The project will involve the design and evaluation of methodologies of synthesis tools for reliable digital circuits and will benefit from initial results achieved as part of the i-RISC project(www.i-risc.eu). The ideal candidate will have interest in coding and information theory, digital logic synthesis, design automation for reliability and will have the opportunity to spend a 12 week internship at University College Cork, Ireland in summer 2016.