Photonic Systems Brown Bag Seminar Series

Thursday, April 5, 2007

12 noon , RLE Haus Conf. Room 36-428

“Design of SiGe Photodiodes in Strict 65nm Bulk CMOS”

Jason Orcutt

As diminishing single core processor performance and further CMOS scaling push chipmakers towards multi-core architectures, the power efficiency and bandwidth density of electrical interconnects is becoming a limiting factor in total system performance. Recent work in silicon photonics shows that the energy efficiency and bandwidth density of photonic links could greatly exceed even the most optimistic predictions for scaled electrical links. However, for this promise to be realized, silicon photonics must move to the realm of CMOS photonics. This means that not only must the materials used be compatible, but also the processing steps used to create the devices must be the steps of the CMOS fab, which have been highly optimized for mosfet production.

In this talk, I will highlight the specific problem of making a photodiode out of the existing PFET source/drain SiGe in a 65nm bulk CMOS flow. The design goal is to make a low-capacitance, high-efficiency photodiode that can be operated at a 10Gb/s data rate. However, the unique constraints imposed by the existing process steps forces us into a new design space that produces a very strange result that more closely resembles a solar cell than a high-speed detector. To figure out whether or not we can still meet our design goals, I will introduce the relevant physical processes that we must consider and present device simulations using Synopsys’s Sentaurus TCAD software. Additionally, to better understand how this proposed structure differs from more traditional photodiodes, I will introduce the talk by reviewing the principles of operation of a more traditional “silicon photonics” Ge-on-Si vertical p-i-n photodiode.