Integrated Systems Group | Prof. Vladimir Stojanovic
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Professor Vladimir Stojanovic

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Vladimir Stojanovic
Associate Professor of Electrical Engineering

Publications

Books and Chapters

Journals and Magazines

Conference papers

Patents

Talks

Tutorials and Short Courses

Google Scholar Citations


Publications

Books and Chapters

  • J.S. Orcutt, R.J. Ram, and V. Stojanović, “CMOS Photonics for High Performance Interconnects,” a chapter in Optical_Fiber Telecommunications VI, Elsevier, 2013, in press.
  • C. Batten, A. Joshi, V. Stojanović, and K. Asanović, “Designing Nanophotonic Interconnection Networks,” a chapter in Integrated Optical Interconnect Architectures and Applications in Embedded Systems, Springer, 2013.
  • D. Oh, S. Chang, J. Ren and V. Stojanović, “Link BER Modeling and Simulation,” a chapter in High-Speed Signaling Analysis, Modeling, and Budgeting, Prentice Hall, 2011.
  • V. G. Oklobdzija, V. M. Stojanović, D. M. Marković, N. M. Nedović, Digital System Clocking: High-Performance and Low-Power Aspects, Wiley-IEEE Press, January 2003

Journal and Magazine publications

  1. O. Salehi-Abari, F. Lim, F. Chen, and Vladimir Stojanović, “Why Analog-to-Information Converters Suffer in High-Bandwidth Sparse Signal Applications,” to appear in IEEE Transactions on Circuits and Systems – I, 12 pages.(paper)
  2. F. Lim and V. Stojanović, “On U-Statistics and Compressed Sensing II: Non-Asymptotic Worst-Case Analysis,” to appear in IEEE Transactions on Signal Processing, 26 pages.(paper)
  3. F. Lim and V. Stojanović, “On U-Statistics and Compressed Sensing I: Non-Asymptotic Average-Case Analysis,” to appear in IEEE Transactions on Signal Processing, 34 pages.(paper)
  4. F. Chen, F. Lim, O. Salehi-Abari, A. Chandrakasan, and V. Stojanović,” Energy Aware Design of Compressed Sensing Systems for Wireless Sensors under Performance and Reliability Constraints,“ IEEE Transactions on Circuits and Systems - I, vol.60, no.3, pp.650-661, March 2013.(paper)
  5. Y. Li, Z. Li, O. Uyar, Y. Avniel, A. Megretski, and V. Stojanović, “High-throughput Signal Component Separator for Asymmetric Multi-level Outphasing Power Amplifiers” IEEE Journal of Solid-State Circuits, vol.48, no.2, pp.369-380, Feb. 2013.(paper)
  6. M. Zhang, V. Stojanović and P. Ampadu, “Reliable Ultra-Low Voltage Cache Design for Many-Core Systems”, IEEE Transactions on Circuits and Systems – II: Express Briefs, vol.59, no.12, pp.858-862, Dec. 2012.(paper)
  7. C. Batten, A. Joshi, V. Stojanovic and K. Asanovic, “Designing Chip-Level Nanophotonic Interconnection Networks [Invited],” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 137-153, June 2012.(paper)
  8. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, "A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI [Invited]," IEEE Journal of Solid-State Circuits, vol. 47, no. 7, 10 pages, July 2012. (paper)
  9. J.S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram and V. Stojanovic, “An Open Foundry Platform for High-Performance Electronic-Photonic Integration,” Optics Express, vol. 20, no. 11, pp. 12222-12232, May 2012 . (paper)
  10. T.-J. K. Liu, D. Markovic, V. Stojanovic and E. Alon, "The Relay Reborn [Invited],” IEEE Spectrum, vol. 49, no. 4, pp. 40-43, April 2012. (paper)
  11. J.S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanovic, and R. J. Ram, “Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process,” Optics Express, vol. 20, no. 7, pp. 7243–7254, March 2012. (paper)
  12. F. Chen, A.P. Chandrakasan, and V. Stojanovic, “Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 744-756, March 2012. (paper)
  13. R. Sredojevic and V. Stojanovic, “Fully-Digital Transmit Equalizer with Dynamic Impedance Modulation [Invited]”, IEEE of Journal Solid-State Circuits, vol. 46, no. 8, pp. 1857-1869 , August 2011. (paper)
  14. S.D. Vamvakos, V. Stojanovic, and B. Nikolic, “Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis,” IEEE Transactions on Circuits and Systems-I, vol. 58, no. 6, pp. 1211-1224, June 2011. (paper)
  15. S. Song and V. Stojanovic, “A 6.25 Gb/s Voltage-time Conversion Based Fractionally Spaced Linear Equalization Receiver for High-speed Links,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1183-1197, May 2011. (paper)
  16. M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, D. Markovic, T.-J. King Liu, E. Alon, and V. Stojanovic, "Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications [Invited]," IEEE Journal of Solid-State Circuits, vol. 46, no. 1, pp. 308-320, Jan. 2011.(paper)
  17. J.S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Optics Express, vol. 19, no. 3, pp. 2335-2346, January 2011.(paper)
  18. H. Kam, T.-J. K. Liu, V. Stojanovic, D. Markovic, and E. Alon, “Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic,” IEEE Transactions on Electron Devices, vol. 58, no. 1, pp. 236-250, January 2011.(paper)
  19. B. Kim and V. Stojanovic, “An Energy-Efficient Equalized Transceiver for RC-Dominant Channels,” IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1186-1197, June 2010.(paper)
  20. B. Bond, Z. Mahmood, R. Sredojevic, Y. Li, A. Megretski, V. Stojanovic, Y. Avniel, and L. Daniel, “Compact Modeling of Nonlinear Analog Circuits using System Identification via Semi-Definite Programming and Robustness Certification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 1149-1162, Aug. 2010.(paper)
  21. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic CMOS silicon photonics [Invited],” IEEE Micro, vol. 29, no. 4, pp. 8-21, 2009. (paper)
  22. N. Blitvic, M. Lee, and V. Stojanovic, “Channel Coding for High-speed Links: A systematic look at code performance and system simulation [Invited],” IEEE Transactions on Advanced Packaging, vol. 2, no. 32, pp. 268-279, 2009. (paper)
  23. K.S. Oh, F. Lambrecht, S. Chang, Q. Lin, J. Ren, C. Yuan, J. Zerbe, and V. Stojanovic, “Accurate system voltage and timing margin simulation in high-speed I/O system design,” IEEE Transactions on Advanced Packaging, vol. 31, no. 4, pp. 722-730, 2008. (paper) (Winner of the 2008 IEEE Transactions on Advanced Packaging Best Paper Award)
  24. B. Kim and V. Stojanovic, “Modeling and design framework: Equalized and repeated interconnects for networks-on-chip [Invited],” IEEE Design & Test of Computers, vol. 25, no. 5, pp. 430-439, 2008. (paper)
  25. E-H. Chen, J. Ren, B. Leibowitz, H. Lee, Q. Lin, D. Oh, F. Lambrecht, V. Stojanovic, Jared Zerbe, and C-K.K. Yang, “Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-based Metric, IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2144–2156, 2008.
  26. A. Amirkhany, A. Abbasfar, J. Savoj, M. Jeeradit, B. Garlepp, V. Stojanovic, and M. A. Horowitz, “A 24Gb/s Software Programmable Analog Multi-Tone Transmitter [Invited],” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 999-1009, 2008.   (paper)
  27. T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kärtner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects [Invited],” Journal of Optical Networking, vol. 6, no. 1, pp. 63-73, 2007. (paper)
  28. V. Stojanovic, A. Ho, B.W. Garlepp, F. Chen, J. Wei, G. Tsang, E. Alon, R.T. Kollipara, C.W. Werner, J.L. Zerbe, and M.A. Horowitz, “Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery [Invited],” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, 2005. (paper)
  29. E. Alon, V. Stojanovic, and M.A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise [Invited],” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 820-828, 2005. (paper)
  30. D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, and R.W. Brodersen, “Methods for true energy-performance optimization,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, 2004. (paper)
  31. J.L. Zerbe, C.W. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W.F. Stonecypher, A. Ho, T.P. Thrush, R.T. Kollipara, M.A. Horowitz, and K.S. Donnelly, “Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell [Invited],” IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2121-2130, 2003. (paper)
  32. C.-K. Yang, V. Stojanovic, S. Modjtahedi, M.A. Horowitz, and W.F. Ellersick, “A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25µm CMOS [Invited],” IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1684-1692, 2001. (paper)
  33. B. Nikolic, V.G. Oklobdzija, V. Stojanovic, W. Jia, J.K. Chiu, and M. Ming-Tak Leung, “Improved sense-amplifier-based flip-flop: design and measurements,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 876-884, 2000. (paper)
  34. V. Stojanovic, and V.G. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 536-548, 1999. (paper)

Conference publications

  1. B.R. Moss, C. Sun, M. Georgas, J. Shainline, J. S Orcutt, J. C. Leu, M. Wade, H. Li, R. Ram, M. A. Popović, and V. Stojanović, “A 1.23 pJ/bit 2.5Gb/s Monolithically-Integrated Optical Carrier-Injection Ring Modulator and All-Digital Driver Circuit in Commercial 45nm SOI,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 126-127, February 2013.(paper)(talk)
  2. J.S. Orcutt, R. Ram, and V. Stojanović, “Integration of Silicon Photonics into Electronic Processes,” SPIE Photonics West, 8 pages, February 2013.(talk)
  3. F. Lim, and V. Stojanovic “Non-Asymptotic Analysis of Compressed Sensing Random Matrices : An U-Statistics Approach,” IEEE International Conference on Communication, Ottawa, Canada, pp. 2511-2515, June 2012.(paper)
  4. J.S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, H. Li, J. Sun, M. Weaver, E. Zgraggen, M. Popovic, R. J. Ram and V. Stojanovic, "Low Loss Waveguide Integration within a Thin-SOI CMOS Foundry," IEEE Optical Interconnects Conference, Santa Fe, NM, 2 pages, May 2012.(paper)(talk)
  5. G. Kurian, C. Sun, O. Chen, J. Miller, L. Wei, J. Michel, D. Antoniadis, L-S. Peh, L. C. Kimerling, V. Stojanovic and A. Agarwal, "Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System using Real Application Workloads," 26th IEEE International Parallel & Distributed Processing Symposium, Shanghai, China, 12 pages, May 2012.(paper)(talk)
  6. C. Sun, O. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh, and V. Stojanovic, "DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling," 6th ACM/IEEE International Symposium on Networks-on-Chip, Lyngby, Denmark, 26 pages, May 2012.(paper)(talk)
  7. E. Timurdogan, E., A. Biberman, D. Trotter, C. Sun, M. Moresco, V. Stojanovic, M. Watts, "Automated Wavelength Recovery for Microring Resonators," Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2012.(paper)
  8. O. Salehi-Abari, F. Chen, F. Lim, and V. Stojanovic, "Performance Trade-offs and Design Limitations of Analog-to-Information Converter Front-Ends," IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, 4 pages, March 2012. (paper)(talk)
  9. J.C. Leu and V. Stojanovic," Injection-Locked Clock Receiver for Monolithic Optical Link in 45nm," Asian Solid-State Circuits Conference, Jeju, Korea, pp. 149-152, November 2011.(paper)(talk)
  10. H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, T-J. K. Liu, and V. Stojanovic," Design and Demonstration of Micro-Electro-Mechanical Relay Multipliers," Asian Solid-State Circuits Conference, Jeju, Korea, pp. 117-120, November 2011. (paper)(talk)
  11. M. Georgas, J.C. Leu, B. Moss, C. Sun, and V. Stojanovic, “Addressing Link-Level Design Tradeoffs for Integrated Photonic Interconnects,” [Invited] IEEE Custom Integrated Circuits Conference, 8 pages, San Jose, CA, September 2011.(paper)(talk)
  12. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic,A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI," European Solid-State Circuits Conference, Helsinki, Finland, pp. 407-410, September 2011.(paper)(talk)
  13. J. S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanovic, and R. J. Ram, “Low-Loss Polysilicon Waveguides Suitable for Integration within a High-Volume Electronics Process,” Optical Society of America - CLEO/QELS Conference, Baltimore, MD, 2 pages, May 2011.(paper)
  14. F. Chen, A. Chandrakasan, and V. Stojanovic, "A Signal-agnostic Compressed Sensing Acquisition System for Wireless and Implantable Sensors," IEEE Custom Integrated Circuits Conference, September, 2010.(paper)
  15. F. Chen, A. Chandrakasan, and V. Stojanovic, "A Low-power Area-efficient Switching Scheme for Charge-sharing DACs in SAR ADCs," IEEE Custom Integrated Circuits Conference, September, 2010.(paper)
  16. H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T.-J. King Liu, E. Alon, V. Stojanovic, and D. Markovic, "Analysis and Demonstration of MEM-Relay Power Gating," IEEE Custom Integrated Circuits Conference, September, 2010.(paper)
  17. R. Sredojevic and V. Stojanovic, “Digital Link Pre-emphasis with Dynamic Driver Impedance Modulation”, IEEE Custom Integrated Circuits Conference, San Jose, CA, September 2010.(paper)(talk)
  18. S. Beamer, C. Sun, Y-J. Kwon, A. Joshi, C. Batten, V. Stojanovic, and K. Asanovic, ”Re-architecting DRAM with Monolithically Integrated Silicon Photonics,” 37th International Symposium on Computer Architecture (ISCA-37), Saint-Malo, France, pp. 129-140, June 2010.(paper) (talk)
  19. V. Stojanovic, A. Joshi, C. Batten, Y-J. Kwon, S. Beamer, C. Sun, and K. Asanovic, “Design-space Exploration for CMOS Photonic Processor Networks,” [Invited] Optical Fiber Communication Conference, San Diego, CA, pp. 1-3, March 2010.(paper)(talk)
  20. F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.-J. King Liu, D. Markovic, V. Stojanovic, and E. Alon, "Demonstration of Integrated Mico-Electro-Mechanical (MEM) Switch Circuits for VLSI Applications," IEEE International Solid-State Circuits Conference, pp. 150-151, February 2010. (paper)(talk) (Winner of the 2010 ISSCC Jack Raper Award for Outstanding Technology-Directions Paper)
  21. J. S. Orcutt, A. Khilo, M. A. Popovic, C. W. Holzwarth, H. Li, J. Sun, B. Moss, M. S. Dahlem, E. P. Ippen, J. L. Hoyt, V. Stojanovic, F. X. Kartner, H. I. Smith, R. J. Ram, “Photonic integration in a commercial scaled bulk-CMOS process,” IEEE International Conference on Photonics in Switching, Pisa, Italy, pp. 1-2, September 2009. (paper)
  22. F. Chen, A. Chandrakasan, and V. Stojanovic, "An Oscilloscope Array for High-Impedance Device Characterization," IEEE European Solid-State Circuits Conference, Athens, Greece, September 14-18, 2009. (paper)(talk)
  23. S.D. Vamvakos, V. Stojanovic, and B. Nikolic, “Discrete-time, Cyclostationary Phase-Locked Loop Model for Jitter Analysis,” IEEE Custom Integrated Circuits Conference, San Jose, CA, 4 pages, September 2009.(paper)(talk)
  24. A. Joshi, B. Kim, and V. Stojanovic,”Designing Energy-efficient Low-diameter On-chip Networks with Equalized Interconnects,” IEEE Symposium on High-Performance Interconnects, New York, NY, 10 pages, August 2009. (paper)(talk)
  25. Y. Li and V. Stojanovic, “Yield-driven Iterative Robust Circuit Optimization Algorithm,” ACM/IEEE Design Automation Conference, San Francisco, CA, 6 pages, July 2009. (paper)(talk)
  26. S. Song, B. Kim, and V. Stojanovic, “A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 222-223, June 2009. (paper)(talk)
  27. V. Stojanovic, A. Joshi, C. Batten, Y-J. Kwon, K. Asanovic, “Manycore Processor Networks with Monolithic Integrated CMOS Photonics,” Optical Society of America - CLEO/QELS Conference [Invited], Baltimore, MD, 2 pages, June 2009. (paper)(talk)
  28. S. Beamer, K. Asanovic, C. Batten, A. Joshi, and V. Stojanovic, “Designing multi-socket systems using silicon photonics,” in Proceedings of the 23rd International Conference on Supercomputing, Yorktown Heights, NY, pp. 521-522, June 2009. (paper)
  29. A. Joshi, C. Batten, Y-J. Kwon, S. Beamer, K. Asanovic, and V. Stojanovic, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, CA, pp. 124-133, May 2009.
    (paper)(talk)
  30. B. Kim and V. Stojanovic, "A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmitter Filter and Transimpedance Receiver in 90nm CMOS Technology,"IEEE International Solid-State Circuit Conference, February 2009.
    (paper)(talk)
  31. R. Sredojevic and V. Stojanovic, “Optimization-based Framework for Simultaneous Circuit and System Design-Space Exploration: A High-Speed Link Example,” IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 314-321, November 2008. (paper)(talk) (Winner of 2008 IEEE/ACM William J. McCalla Best Paper Award)
  32. F. Chen, H. Kam, D. Markovic, T.J. King, V. Stojanovic, and E. Alon, “Integrated Circuit Design with NEM Relays,” to appear in IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, 6 pages, November 2008.    (paper)(talk)
  33. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic silicon photonics,” to appear in IEEE Symposium on High-Performance Interconnects, Stanford, CA, 10 pages, August 2008. (paper)(talk)
  34. N. Blitvic, L. Zheng, and V. Stojanovic ,”Low-complexity Pattern-eliminating Codes for ISI-limited Channels,” IEEE International Communications Conference, Beijing, China, 7 pages, pp. 1214-1219, May 2008. (paper)(talk)
  35. C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
  36. J. S. Orcutt, A. Khilo, M. A. Popovic, C. W. Holzwarth, B. Moss, H. Li, M. S. Dahlem, T. D. Bonifield, F. X. Kärtner, E. P. Ippen, J. L. Hoyt, R. J. Ram, and V. Stojanovic,Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
  37. B. Kim and V. Stojanovic, “Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework,” IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, pp. 552-559, November 2007.    (paper)(talk)
  38. F. Chen, A. Joshi, V.Stojanovic, and A. Chandrakasan, “Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications,” ACM International Conference on Nano-Networks, Catania, Italy, p.8, September 2007.    (paper)(talk)
  39. A. Amirkhany, A. Abbasfar, V. Stojanovic, and M.A. Horowitz, “Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links,” IEEE International Conference on Communications, Glasgow, Scotland, pp. 2693-2698, June 2007. (paper)
  40. N. Blitvic and V. Stojanovic, “Statistical Simulator for Block Coded Channels with Long Residual Interference,” IEEE International Conference on Communications, Glasgow, Scotland, pp. 6287-6294, June 2007. (paper)(talk)
  41. A. Amirkhany, A. Abbasfar, J. Savoj, M. Jeeradit, B. Garlepp, V. Stojanovic, and M. Horowitz, “24 Gbps, Software Programmable Multi-Channel Transmitter,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 38-39, June 2007.   (paper)(talk)
  42. E-H. Chen, J. Ren, J.Zerbe, B. Leibowitz, H. Lee, V. Stojanovic, and C-K. K. Yang, “BER-based Adaptation of I/O Link Equalizers,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 36-37, June 2007. (paper)
  43. J. Ren, H. Lee, Q. Lin, B. Leibowitz, E-H. Chen, D. Oh, F. Lambrecht, V. Stojanovic, C-K. K. Yang, and J.Zerbe, “Precursor ISI Reduction in High-Speed I/O,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 134-135, June 2007. (paper)
  44. B.S. Leibowitz, J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A. Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Daly, F. Heaton, B.W. Gariepp, C.W. Werner, N. Nguyen, V. Stojanovic, and J.L. Zerbe, “A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 228-599, February 2007. (paper)
  45. A. Amirkhany, A. Abbasfar, V. Stojanovic, and M.A. Horowitz, “Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links,” IEEE Global Telecommunications Conference, San Francisco, CA, pp. 1-6, November 2006.(paper)(talk)
  46. H. Hatamkhani, F. Lambrecht, V. Stojanovic, and C.K. Yang, “Power-Centric Design of High-Speed I/Os,” ACM/IEEE Design Automation Conference, Anaheim, CA, pp. 867-872, July 2006. (paper)(talk)
  47. S. Vamvakos, V. Stojanovic, J. Zerbe, C. Werner, D. Draper, and B. Nikolic, “PLL On-Chip Jitter Measurement: Analysis and Design,” IEEE Symposium on VLSI Circuits Symposium, Honolulu, HI, pp. 73-74, June 2006. (paper)(talk)
  48. J. Ren, H. Lee, D. Oh, B. Leibowitz, V. Stojanovic, J. Zerbe, and N. Nguyen, “Performance Analysis of Edge-based DFE,” 15th Topical Meeting on  Electrical Performance of Electronic Packaging, Scottsdale, AZ, pp. 265-268, October 2006.     (paper)(talk)
  49. F. Lambrecht, Q. Lin, S. Chang, D. Oh, C. Yuan, and V. Stojanovic, “Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs,” 15th Topical Meeting on  Electrical Performance of Electronic Packaging, Scottsdale, AZ, pp. 171-174, October 2006. (paper)
  50. C. Werner, C. Hoyer, A. Ho, M. Jeeradit, F. Chen, B. Garlepp, W. Stonecypher, S. Li, A. Bansal, A. Agarwal, E. Alon, V. Stojanovic, and J. Zerbe, “Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system,” IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 704-711, September 2005. (paper)
  51. B. Garlepp, A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, T. Thrush, A. Agarwal, and J. Zerbe, “A 1-10 Gbps PAM2, PAM4, PAM2 partial response receiver analog front end with dynamic sampler swapping capability for backplane serial communications,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 376-379, June 2005. (paper)
  52. E. Alon, V. Stojanovic, J.M. Kahn, S. Boyd, and M. Horowitz, “Equalization of modal dispersion in multimode fiber using spatial light modulators,” IEEE Global Telecommunications Conference, Dallas, TX, vol. 2, pp. 1023-1029, November 2004. (paper)
  53. A. Amirkhany, V. Stojanovic, and M.A. Horowitz, “Multi-tone signaling for high-speed backplane electrical links,” IEEE Global Telecommunications Conference, Dallas, TX, vol. 2, pp. 1111-1117, November 2004. (paper)
  54. V. Stojanovic, A. Amirkhany, and M.A. Horowitz, “Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication,” IEEE International Conference on Communications, Paris, France, vol. 5, pp. 2799-2806, June 2004. (paper)(talk)
  55. E. Alon, V. Stojanovic, and M. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE Symposium on VLSI Circuits, Honolulu, HI, pp. 102-105, June 2004. (paper)(talk)
  56. A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, and M.A. Horowitz, “Common-mode backchannel signaling system for differential high-speed links,” IEEE Symposium on VLSI Circuits, Honolulu, HI, pp. 352-355, June 2004.
    (paper)(talk
    )
  57. V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, E. Alon, C. Werner, J. Zerbe, and M.A. Horowitz, “Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver,” IEEE Symposium on VLSI Circuits, Honolulu, HI, pp. 348-351, June 2004. (paper)(talk)
  58. J.L. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara, G.J. Yeh, M. Horowitz, and K. Donnelly, “Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 80-479, February 2003. (paper)
  59. V. Stojanovic and M. Horowitz, “Modeling and analysis of high-speed links [Invited],” IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 589-594, September 2003. 
    (paper)(talk
    )
  60. R.W. Brodersen, M.A. Horowitz, D. Markovic, B. Nikolic, and V. Stojanovic, “Methods for true power minimization,” IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 35-42, November 2002. (paper)(talk)
  61. V. Stojanovic, D. Markovic, B. Nikolic, M.A. Horowitz, and R.W. Brodersen. “Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization,” European Solid-State Circuits Conference, Florence, Italy, pp. 211-214, September 2002. (paper)(talk)
  62. V. Stojanovic, G. Ginis. and M.A. Horowitz, “Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver,” IEEE International Conference on Communications, New York, NY, vol. 3, pp. 1934-1939, May 2002. (paper)(talk)
  63. W. Ellersick, C.-K. Yang, V. Stojanovic, S. Modjtahedi, and M.A. Horowitz, “A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25µm CMOS,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 58-59, 430, February 2001. (paper)(talk)
  64. B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, and M. Leung, “Sense amplifier-based flip-flop,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 282-283, February 1999. (paper)
  65. V. Stojanovic, V. Oklobdzija, and R. Bajwa, “Comparative analysis of latches and flip-flops for high-performance systems,” International Conference on Computer Design, Austin, TX, pp. 264-269, October 1998. (paper)
  66. V. Stojanovic, V.G. Oklobdzija, and R. Bajwa, “A unified approach in the analysis of latches and flip-flops for low-power systems,” International Symposium on Low Power Electronics and Design, Monterey, CA, pp. 227-232, August 1998. (paper)

Patents

 

  1. J. L. Zerbe, V. Stojanovic, F. Chen, “Selectable-tap equalizer,” United States Patent 8,023,584, issued September 20, 2011.

  2. F. F. Chen, V. Stojanovic, “Equalizing transceiver with reduced parasitic capacitance,” United States Patent 7,982,507, issued July 19, 2011.
  3. A. Abbasfar, A. Amirkhany, V. Stojanovic, M. Horowitz, “Linear Transformation Circuit,” United States Patent 7,925,686, issued April 12, 2011.
  4. V. Stojanovic, A. Amirkhany, J. L. Zerbe, “Adjustable dual-band link,” United States Patent 7,907,676, issued March 15, 2011.
  5. J. L. Zerbe, V. Stojanovic, F. Chen, “Selectable-tap equalizer,” United States Patent 7,873,115, issued January 18, 2011.
  6. J. L. Zerbe, V. Stojanovic, F. Chen, “Selectable-tap equalizer,” United States Patent 7,860,156, issued December 28, 2010.
  7. V. M. Stojanovic, A. Amirkhany, J. L. Zerbe, “Multi-tone system with oversampled precoders,” United States Patent 7,817,743, issued October 19, 2010.
  8. V. M. Stojanovic, M. A. Horowitz, J. L. Zerbe, A. Bessios, A. C. C. Ho, J. C. Wei, G. Tsang, B. W. Garlepp, “Partial response receiver,” United States Patent 7,715,501, issued May 11, 2010.
  9. E. Alon, V. Stojanovic, A. Amirkhany, “Digital Transmitter with data stream transformation circuitry,” United States Patent 7,711,063, issued May 4, 2010.
  10. A. Ho, V. Stojanovic, B. W. Garlepp, F. F. Chen “Margin test methods and circuits,” United States Patent 7,627,029, issued December 1, 2009.
  11. V. Stojanovic, A. Amirkhany, J. L. Zerbe, “Adjustable dual-band link,” United States Patent 7,599,422, issued October 6, 2009.
  12. J. L. Zerbe, V. Stojanovic, F. Chen, “Selectable-tap equalizer,” United States Patent 7,508,871, issued March 24, 2009.
  13. A. Aliazam, A. Amirkhany, V. Stojanovic, M. Horowitz, “Linear Transformation Circuit,” United States Patent 7,483,491, issued January 27, 2009.

  14. V. Stojanovic, A. Amirkhany, J. L. Zerbe, “Adjustable dual-band link,” United States Patent 7,450,629, issued November 11, 2008.

  15. B. W. Garlepp, J. L. Zerbe, M. Jeeradit, V. Stojanovic, “Partial response receiver with clock data recovery,” United States Patent 7,433,397, issued October 7, 2008.
  16. V. M. Stojanovic, A. C. C. Ho, A. Bessios, F. F. Chen, E. Alon, M. A. Horowitz, “High speed signaling system with adaptive transmit pre-emphasis,” United States Patent 7,423,454, issued September 9, 2008.
  17. J. L. Zerbe, V. Stojanovic, F. Chen, “Auto-configured equalizer,” United States Patent 7,362,800, issued April 22, 2008.

  18. F. F. Chen, V. Stojanovic, “Equalizing transceiver with reduced parasitic capacitance,” United States Patent 7,348,811, issued March 25, 2008.
  19. V. Stojanovic, A. Amirkhany, J. L. Zerbe, “Adjustable dual-band link,” United States Patent 7,349,484, issued March 25, 2008

  20. A. Ho, V. Stojanovic, F. Chen, E. Alon, M. Horowitz, “Noise-tolerant signaling schemes supporting simplified timing and data recovery,” United States Patent 7,292,637, issued November 6, 2007

  21. J. L. Zerbe, V. Stojanovic, F. Chen, “Selectable-tap equalizer,” United States Patent 7,292,629, issued November 6, 2007

  22. V. Stojanovic, A. Ho, F. Chen, B. Garlepp, “Offset cancellation in a multi-level signaling system,” United States Patent 7,233,164, issued Jun 19, 2007.
  23. V. Stojanovic, A. Ho, A. Bessios, F. Chen, E. Alon, M. Horowitz, “High Speed Signaling System with Adaptive Transmit Pre-Emphasis and Reflection Cancellation,” United States Patent 7,199,615, issued April 3, 2007.
  24. J. Kahn, M. Horowitz, E. Alon, V. Stojanovic, “Adaptive control for mitigating interference in a multimode transmission medium,” United States Patent 7,194,155, issued March 20, 2007.
  25. A. Ho, V. Stojanovic “Signal receiver with data precessing function,” United States Patent 7,176,721, issued February 13, 2007.
  26. A. Amirkhany, V. Stojanovic, E. Alon, J. Zerbe, M. Horowitz, “Linear Transformation Circuits,” United States Patent 7,133,463, issued November 7, 2006.
  27. V. Stojanovic, A. Ho, A. Bessios, F. Chen, E. Alon, M. Horowitz, “High Speed Signaling System with Adaptive Transmit Pre-Emphasis,” United States Patent 7,126,378, issued October 24, 2006.
  28. E. Alon, B. Garlepp, V. Stojanovic, A. Ho, F. Chen, “Circuit Calibration System and Method,” United States Patent 7,126,510, issued October 24, 2006.
  29. V. Stojanovic, “Data-level Clock Recovery,” United States Patent 7,092,472, issued August 15, 2006.
  30. V. Stojanovic, A. Ho, A. Bessios, F. Chen, E. Alon, M. Horowitz, “High Speed Signaling System with Adaptive Transmit Pre-Emphasis and Reflection Cancellation,” United States Patent 7,030,657, issued April 18, 2006.
  31. J. L. Zerbe, V. M. Stojanovic, M. A. Horowitz, P. S. Chau, “Input/output circuit with on-chip inductor to reduce parasitic capacitance,” United States Patent 7,005,939, issued February 28, 2006.
  32. F. F. Chen, V. Stojanovic, “Equalizing transceiver with reduced parasitic capacitance,” United States Patent 6,982,587, issued January 3, 2006.
  33. V. G. Oklobdzija, V. Stojanovic, “Flip-Flop,” United States Patent 6,232,810, issued May 15, 2001.

INVITED tALKS

February 2013, “Computer Chips that Communicate with Light: Building VLSI Chips with Integrated Silicon-Photonics,” UC Berkeley EECS Department Seminar, also at Yale University EE Department Seminar.

 

October 2012, “Building Modern Integrated Systems: A Cross-cut Approach,” University of Pennsylvania, ESE Department Seminar, also December 2012 Columbia University, EE Colloquium, also February 2013 UC San Diego EE Department Seminar.

 

April 2012, “Designing VLSI Interconnects with Monolithically Integrated Silicon-Photonics,” Solid-State Circuits Society Distinguished Lecture at the Seventh Annual Workshop on Semiconductors and Micro & Nano Technology (SEMINATEC), Sao Paolo, Brazil, also November 2012, Solid-State Circuits Society Santa Clara Chapter Distinguished Lecture, Santa Clara, CA.

November 2011, “Scaling with photonics inside processors and memory,” Disruptive Technologies Panel, session on Integrated Silicon Photonic Technologies in Future Computing Systems: Impact on Hardware, Software, and Applications, at 2011 Supercomputing Conference, Seattle, WA.

June 2011, “Designing VLSI Circuits and Systems with Nano Electro-Mechanical Relays,” 2011 CMOS Emerging Technologies Workshop, Whistler, Canada.

April 2011, “Building Modern Integrated Systems: A Cross-cut Approach (The Electrical, The Optical and The Mechanical),” EECS Department Seminar, UC Berkeley, also June 2011, UC San Diego EE Department Seminar, Carnegie Mellon ECE Department Seminar and University of Illionois, Urbana-Champaign ECE Department Seminar, also July 2011 Cornell University, ECE Department Seminar, also October 2011 Columbia University, EE Department Seminar, also January 2012 MIT-Japan Conference, also March 2012 University of Southern California,

December 2010, “EOS: A Monolithic CMOS Photonic Platform,” Workshop on the Interaction between Nanophotonic Devices and Systems, MICRO-43: International Symposium on Microarchitecture, also December 2010, at Berkeley Wireless Research Center Seminar, also January 2011, at UCLA EE Department Seminar.

May 2010, “Looking Beyond CMOS: Integrated Circuit Design with Nano Electro-Mechanical Switches,” 27th International Conference on Microelectronics, Nis, Serbia; also May 2010, “Minimum Energy Electronic Systems” joint NSF/SRC/ATIC Forum, Abu-Dhabi, UAE; also June, 2010, 21st Irish Signals and Systems Conference, Cork, Ireland.

March 2010, “Design-Space Exploration for CMOS Photonic Processor Networks,” 2010 Optical Fiber Communication Conference, San Diego, CA.

January 2010, ”CMOS Photonic Processor-Memory Networks,” 2010 IEEE/LEOS Winter Topical Meeting, Majorca, Spain.

June 2009, “Manycore Processor Networks with Monolithic Integrated CMOS Photonics,” Optical Society of America - CLEO/QELS Conference, Baltimore, MD.

March 2009, “CMOS-photonics in Manycore Processor Systems,” Optical Fiber Conference 2009 Panel, San Diego, CA.

March 2009, “Optimization-based Framework for Simultaneous Circuit-and-System Design-space Exploration of Analog/Mixed-Signal Front-ends: A High-speed Link Example,” IEEE Council on Electronic Design Automation Distinguished Speakers Series, Berkeley, CA. (video)

May 2008, “The Challenges of CMOS Photonics and Electronics for Enhanced Microprocessor Performance,” 52nd International Conference on Electron, Ion, Photon Beam and Nanofabrication Technology, Portland, OR.

May 2008, “Circuit-to-System Design-Space Exploration Methodology: Interconnect examples,” 2nd IBM Conference on Analog Design, Technology, Modeling, Tools and Test, IBM T. J. Watson Research Laboratory, Yorktown Heights,NY.

October 2007, “The Interconnect Problem: From Emerging Devices to Energy-efficient Networks,” IBM T.J. Watson Research Laboratory Seminar; also January 2008 at University of Hawaii, Electrical Engineering Department Seminar, also July 2008 at University of Belgrade, Electrical Engineering Department Seminar, Belgrade, Serbia, and University of Niš, Electrical Engineering Department Seminar, Niš, Serbia.

October 2007, “High-Speed Links: A new field in high-throughput, energy-efficient communications,” IEEE ComSoc Boston Chapter Seminar, Boston, MA. September 2007, “Equalization and modulation in high-speed I/O: Architectures and circuits,” IEEE Custom Integrated Circuits Conference tutorial session, San Jose, CA.

April 2007, “Inside the Box: A new hope for optics?,” Ideastream Deshpande Center Symposium, Boston, MA.

December 2005, “System Design with Nano Devices?” NSF/SRC workshop on Novel, Short-Range Information Transfer Mechanisms, Arlington, VA.

April 2005, “Design of High-Speed Links: A look at Modern VLSI Design,” Harvard University, Division of Engineering and Applied Sciences Seminar Series; also October 2005 at Caltech University, Electrical Engineering Department Seminar; also January 2006 at RPI, Electrical Engineering Department Seminar; also April 2006 at IBM T.J. Watson Research Laboratory Seminar and Columbia University Electrical Engineering Department Seminar; also October 2006 at Cornell University Electrical Engineering Department Seminar and Tufts University Electrical Engineering Department Seminar.

May 2005, “High-speed serial links: Design Trends and Challenges” 17th Annual LEOS Workshop on Interconnections within High-Speed Digital Systems, Santa Fe, NM.

 

TUTORIALS and SHORT COURSES

November 2011, “Nano-Electro-Mechanical Relay Integrated Circuits and Technology,” special Tutorial session at the 2011 IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA.

(part 1)(part 2)(part 3)

August 2010, “Silicon Photonics and Memories,” tutorial at 2010 Hot Chips Symposium, Stanford, CA.

February 2010, “Design of Energy-Efficient On-Chip Networks,” tutorial at 2010 IEEE International Solid-State Circuits Conference, San Francisco, CA.

June 2008, MIT 6.22s Short Course on High-Speed Link Design

(day 1)(day 2)(day 3)

January 2007, “A systems approach to building modern high-speed links,” IEEE Distinguished Lecturer Short-Course Series, National Taiwan University, Department of Electrical Engineering, Taipei, Taiwan; also at National Chiao Tung University Department of Electrical Engineering, Hsinchu, Taiwan.

 

 

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