Integrated Systems Group | Prof. Vladimir Stojanovic
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Professor Vladimir Stojanovic

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Vladimir Stojanovic
Assistant Professor of Electrical Engineering

Publications

Books

Journals

Conference papers

Patents

Talks


Publications

Books

  • V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovc, N. M. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects, Wiley-IEEE Press, January 2003

Journal publications

    1. Kim, B. and V. Stojanovic, “Modeling and Design Framework: Equalized and Repeated Interconnects for Networks-on-Chip [Invited],” to appear in IEEE Design & Test of Computers, 8 pages, 2008. (paper)
    2. Chen, E-H., J. Ren, B. Leibowitz, H. Lee, Q. Lin, D. Oh, F. Lambrecht, V. Stojanovic, Jared Zerbe, and C-K.K. Yang, “Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-based Metric, to appear in IEEE Journal of Solid-State Circuits, 32 pages, 2008.
    3. Oh, K. S., F. Lambrecht, S. Chang, Q. Lin, J. Ren, C. Yuan, J. Zerbe, and V. Stojanovic, “Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Design,” to appear in IEEE Transactions on Advanced Packaging, 10 pages, 2008.
    4. Amirkhany, A., A. Abbasfar, J. Savoj, M. Jeeradit, B. Garlepp, V. Stojanovic, and M. A. Horowitz, “A 24Gb/s Software Programmable Analog Multi-Tone Transmitter,” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 999-1009, 2008.   (paper)
    5. Barwicz, T., H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kärtner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects [Invited],” Journal of Optical Networking, vol. 6, no. 1, pp. 63-73, 2007. (paper)
    6. Stojanovic, V., A. Ho, B.W. Garlepp, F. Chen, J. Wei, G. Tsang, E. Alon, R.T. Kollipara, C.W. Werner, J.L. Zerbe, and M.A. Horowitz, “Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, 2005. (paper)
    7. Alon, E., V. Stojanovic, and M.A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 820-828, 2005. (paper)
    8. Markovic, D., V. Stojanovic, B. Nikolic, M.A. Horowitz, and R.W. Brodersen, “Methods for true energy-performance optimization,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, 2004. (paper)
    9. Zerbe, J.L., C.W. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W.F. Stonecypher, A. Ho, T.P. Thrush, R.T. Kollipara, M.A. Horowitz, and K.S. Donnelly, “Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell,” IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2121-2130, 2003. (paper)
    10. Yang, C.-K., V. Stojanovic, S. Modjtahedi, M.A. Horowitz, and W.F. Ellersick, “A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1684-1692, 2001. (paper)
    11. Nikolic, B., V.G. Oklobdzija, V. Stojanovic, W. Jia, J.K. Chiu, and M. Ming-Tak Leung, “Improved sense-amplifier-based flip-flop: design and measurements,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 876-884, 2000. (paper)
    12. Stojanovic, V. and V.G. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 536-548, 1999. (paper)

Conference publications

    1. Sredojevic, R. and V. Stojanovic, “Optimization-based Framework for Simultaneous Circuit and System Design-Space Exploration: A High-Speed Link Example,” to appear in IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 8 pages, November 2008. (paper)(talk)
    2. Chen, F., H. Kam, D. Markovic, T.J. King, V. Stojanovic, and E. Alon, “Integrated Circuit Design with NEM Relays,” to appear in IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, 6 pages, November 2008.    (paper)(talk)
    3. Batten, C., A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic silicon photonics,” to appear in IEEE Symposium on High-Performance Interconnects, Stanford, CA, 10 pages, August 2008. (paper)(talk)
    4. Blitvic, N. , L. Zheng, and V. Stojanovic ,”Low-complexity Pattern-eliminating Codes for ISI-limited Channels,” IEEE International Communications Conference, Beijing, China, 7 pages, pp. 1214-1219, May 2008. (paper)(talk)
    5. Holzwarth, C. W., J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
    6. Orcutt, J. S., A. Khilo, M. A. Popovic, C. W. Holzwarth, B. Moss, H. Li, M. S. Dahlem, T. D. Bonifield, F. X. Kärtner, E. P. Ippen, J. L. Hoyt, R. J. Ram, and V. Stojanovic, “Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
    7. Kim, B. and V. Stojanovic, “Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework,” IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, pp. 552-559, November 2007.    (paper)(talk)
    8. Chen, F., A. Joshi, V.Stojanovic, and A. Chandrakasan, “Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications,” ACM International Conference on Nano-Networks, Catania, Italy, p.8, September 2007.    (paper)(talk)
    9. Amirkhany, A., A. Abbasfar, V. Stojanovic, and M.A. Horowitz, “Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links,” IEEE International Conference on Communications, Glasgow, Scotland, pp. 2693-2698, June 2007. (paper)
    10. Blitvic, N. and V. Stojanovic, “Statistical Simulator for Block Coded Channels with Long Residual Interference,” IEEE International Conference on Communications, Glasgow, Scotland, pp. 6287-6294, June 2007. (paper)(talk)
    11. Amirkhany, A., A. Abbasfar, J. Savoj, M. Jeeradit, B. Garlepp, V. Stojanovic, and M. Horowitz, “24 Gbps, Software Programmable Multi-Channel Transmitter,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 38-39, June 2007.   (paper)(talk)
    12. Chen, E-H., J. Ren, J.Zerbe, B. Leibowitz, H. Lee, V. Stojanovic, and C-K. K. Yang, “BER-based Adaptation of I/O Link Equalizers,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 36-37, June 2007. (paper)
    13. Ren, J., H. Lee, Q. Lin, B. Leibowitz, E-H. Chen, D. Oh, F. Lambrecht, V. Stojanovic, C-K. K. Yang, and J.Zerbe, “Precursor ISI Reduction in High-Speed I/O,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 134-135, June 2007. (paper)
    14. Leibowitz, B.S., J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A. Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Daly, F. Heaton, B.W. Gariepp, C.W. Werner, N. Nguyen, V. Stojanovic, and J.L. Zerbe, “A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 228-599, February 2007. (paper)
    15. Amirkhany, A., A. Abbasfar, V. Stojanovic, and M.A. Horowitz, “Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links,” IEEE Global Telecommunications Conference, San Francisco, CA, pp. 1-6, November 2006.(paper)(talk)
    16. Hatamkhani, H., F. Lambrecht, V. Stojanovic, and C.K. Yang, “Power-Centric Design of High-Speed I/Os,” ACM/IEEE Design Automation Conference, Anaheim, CA, pp. 867-872, July 2006. (paper)(talk)
    17. Vamvakos, S., V. Stojanovic, J. Zerbe, C. Werner, D. Draper, and B. Nikolic, “PLL On-Chip Jitter Measurement: Analysis and Design,” IEEE Symposium on VLSI Circuits Symposium, Honolulu, HI, pp. 73-74, June 2006. (paper)(talk)
    18. Ren, J., H. Lee, D. Oh, B. Leibowitz, V. Stojanovic, J. Zerbe, and N. Nguyen, “Performance Analysis of Edge-based DFE,” 15th Topical Meeting on  Electrical Performance of Electronic Packaging, Scottsdale, AZ, pp. 265-268, October 2006.     (paper)(talk)
    19. Lambrecht, F., Q. Lin, S. Chang, D. Oh, C. Yuan, and V. Stojanovic, “Accurate System Voltage and Timing Margin Simulation in CDR Based High Speed Designs,” 15th Topical Meeting on  Electrical Performance of Electronic Packaging, Scottsdale, AZ, pp. 171-174, October 2006. (paper)
    20. Werner, C., C. Hoyer, A. Ho, M. Jeeradit, F. Chen, B. Garlepp, W. Stonecypher, S. Li, A. Bansal, A. Agarwal, E. Alon, V. Stojanovic, and J. Zerbe, “Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system,” IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 704-711, September 2005. (paper)
    21. Garlepp, B., A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, T. Thrush, A. Agarwal, and J. Zerbe, “A 1-10 Gbps PAM2, PAM4, PAM2 partial response receiver analog front end with dynamic sampler swapping capability for backplane serial communications,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 376-379, June 2005. (paper)
    22. Alon, E., V. Stojanovic, J.M. Kahn, S. Boyd, and M. Horowitz, “Equalization of modal dispersion in multimode fiber using spatial light modulators,” IEEE Global Telecommunications Conference, Dallas, TX, vol. 2, pp. 1023-1029, November 2004. (paper)
    23. Amirkhany, A., V. Stojanovic, and M.A. Horowitz, “Multi-tone signaling for high-speed backplane electrical links,” IEEE Global Telecommunications Conference, Dallas, TX, vol. 2, pp. 1111-1117, November 2004. (paper)
    24. Stojanovic, V., A. Amirkhany, and M.A. Horowitz, “Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication,” IEEE International Conference on Communications, Paris, France, vol. 5, pp. 2799-2806, June 2004. (paper)(talk)
    25. Alon, E., V. Stojanovic, and M. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE Symposium on VLSI Circuits, Honolulu, HI, pp. 102-105, June 2004. (paper)(talk)
    26. Ho, A., V. Stojanovic, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, and M.A. Horowitz, “Common-mode backchannel signaling system for differential high-speed links,” IEEE Symposium on VLSI Circuits, Honolulu, HI, pp. 352-355, June 2004. (paper)(talk)
    27. Stojanovic, V., A. Ho, B. Garlepp, F. Chen, J. Wei, E. Alon, C. Werner, J. Zerbe, and M.A. Horowitz, “Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver,” IEEE Symposium on VLSI Circuits, Honolulu, HI, pp. 348-351, June 2004. (paper)(talk)
    28. Zerbe, J., C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara, G.J. Yeh, M. Horowitz, and K. Donnelly, “Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 80-479, February 2003. (paper)
    29. Stojanovic V. and M. Horowitz, “Modeling and analysis of high-speed links [Invited],” IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 589-594, September 2003.  (paper)(talk)
    30. Brodersen, R.W., M.A. Horowitz, D. Markovic, B. Nikolic, and V. Stojanovic, “Methods for true power minimization,” IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, pp. 35-42, November 2002.         (paper)(talk)
    31. Stojanovic, V., D. Markovic, B. Nikolic, M.A. Horowitz, and R.W. Brodersen. “Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization,” European Solid-State Circuits Conference, Florence, Italy, pp. 211-214, September 2002. (paper)(talk)
    32. Stojanovic, V., G. Ginis. and M.A. Horowitz, “Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver,” IEEE International Conference on Communications, New York, NY, vol. 3, pp. 1934-1939, May 2002. (paper)(talk)
    33. Ellersick, W., C.-K. Yang, V. Stojanovic, S. Modjtahedi, and M.A. Horowitz, “A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25µm CMOS,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 58-59, 430, February 2001. (paper)(talk)
    34. Nikolic, B., V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, and M. Leung, “Sense amplifier-based flip-flop,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 282-283, February 1999. (paper)
    35. Stojanovic, V., V. Oklobdzija, and R. Bajwa, “Comparative analysis of latches and flip-flops for high-performance systems,” International Conference on Computer Design, Austin, TX, pp. 264-269, October 1998. (paper)
    36. Stojanovic, V., V.G. Oklobdzija, and R. Bajwa, “A unified approach in the analysis of latches and flip-flops for low-power systems,” International Symposium on Low Power Electronics and Design, Monterey, CA, pp. 227-232, August 1998. (paper)

Patents

    1. J. L. Zerbe, V. Stojanovic, F. Chen, “Auto-configured equalizer,” United States Patent 7,362,800, issued April 22, 2008.

    2. F. F. Chen, V. Stojanovic, “Equalizing transceiver with reduced parasitic capacitance,” United States Patent 7,348,811, issued March 25, 2008.

    3. V. Stojanovic, A. Amirkhany, J. L. Zerbe, “Adjustable dual-band link,” United States Patent 7,349,484, issued March 25, 2008

    4. A. Ho, V. Stojanovic, F. Chen, E. Alon, M. Horowitz, “Noise-tolerant signaling schemes supporting simplified timing and data recovery,” United States Patent 7,292,637, issued November 6, 2007

    5. J. L. Zerbe, V. Stojanovic, F. Chen, “Selectable-tap equalizer,” United States Patent 7,292,629, issued November 6, 2007

    6. V. Stojanovic, A. Ho, F. Chen, B. Garlepp, “Offset cancellation in a multi-level signaling system,” United States Patent 7,233,164, issued Jun 19, 2007.
    7. V. Stojanovic, A. Ho, A. Bessios, F. Chen, E. Alon, M. Horowitz, “High Speed Signaling System with Adaptive Transmit Pre-Emphasis and Reflection Cancellation,” United States Patent 7,199,615, issued April 3, 2007.
    8. J. Kahn, M. Horowitz, E. Alon, V. Stojanovic, “Adaptive control for mitigating interference in a multimode transmission medium,” United States Patent 7,194,155, issued March 20, 2007.
    9. A. Ho, V. Stojanovic “Signal receiver with data precessing function,” United States Patent 7,176,721, issued February 13, 2007.
    10. A. Amirkhany, V. Stojanovic, E. Alon, J. Zerbe, M. Horowitz, “Linear Transformation Circuits,” United States Patent 7,133,463, issued November 7, 2006.
    11. V. Stojanovic, A. Ho, A. Bessios, F. Chen, E. Alon, M. Horowitz, “High Speed Signaling System with Adaptive Transmit Pre-Emphasis,” United States Patent 7,126,378, issued October 24, 2006.
    12. E. Alon, B. Garlepp, V. Stojanovic, A. Ho, F. Chen, “Circuit Calibration System and Method,” United States Patent 7,126,510, issued October 24, 2006.
    13. V. Stojanovic, “Data-level Clock Recovery,” United States Patent 7,092,472, issued August 15, 2006.
    14. V. Stojanovic, A. Ho, A. Bessios, F. Chen, E. Alon, M. Horowitz, “High Speed Signaling System with Adaptive Transmit Pre-Emphasis and Reflection Cancellation,” United States Patent 7,030,657, issued April 18, 2006.
    15. J. L. Zerbe, V. M. Stojanovic, M. A. Horowitz, P. S. Chau, “Input/output circuit with on-chip inductor to reduce parasitic capacitance,” United States Patent 7,005,939, issued February 28, 2006.
    16. F. F. Chen, V. Stojanovic, “Equalizing transceiver with reduced parasitic capacitance,” United States Patent 6,982,587, issued January 3, 2006.
    17. V. G. Oklobdzija, V. Stojanovic, “Flip-Flop,” United States Patent 6,232,810, issued May 15, 2001.

tALKS

May 2008, “The Challenges of CMOS Photonics and Electronics for Enhanced Microprocessor Performance,” 52nd International Conference on Electron, Ion, Photon Beam and Nanofabrication Technology, Portland, OR.

May 2008, “Circuit-to-System Design-Space Exploration Methodology: Interconnect examples,” 2nd IBM Conference on Analog Design, Technology, Modeling, Tools and Test, IBM T. J. Watson Research Laboratory, Yorktown Heights,NY.

October 2007, “The Interconnect Problem: From Emerging Devices to Energy-efficient Networks,” IBM T.J. Watson Research Laboratory Seminar; also January 2008 at University of Hawaii, Electrical Engineering Department Seminar, also July 2008 at University of Belgrade, Electrical Engineering Department Seminar, Belgrade, Serbia, and University of Niš, Electrical Engineering Department Seminar, Niš, Serbia.

October 2007, “High-Speed Links: A new field in high-throughput, energy-efficient communications,” IEEE ComSoc Boston Chapter Seminar, Boston, MA. September 2007, “Equalization and modulation in high-speed I/O: Architectures and circuits,” IEEE Custom Integrated Circuits Conference tutorial session, San Jose, CA.

April 2007, “Inside the Box: A new hope for optics?,” Ideastream Deshpande Center Symposium, Boston, MA.

January 2007, “A systems approach to building modern high-speed links,” IEEE Distinguished Lecturer Short-Course Series, National Taiwan University, Department of Electrical Engineering, Taipei, Taiwan; also at National Chiao Tung University Department of Electrical Engineering, Hsinchu, Taiwan.

December 2005, “System Design with Nano Devices?” NSF/SRC workshop on Novel, Short-Range Information Transfer Mechanisms, Arlington, VA.

April 2005, “Design of High-Speed Links: A look at Modern VLSI Design,” Harvard University, Division of Engineering and Applied Sciences Seminar Series; also October 2005 at Caltech University, Electrical Engineering Department Seminar; also January 2006 at RPI, Electrical Engineering Department Seminar; also April 2006 at IBM T.J. Watson Research Laboratory Seminar and Columbia University Electrical Engineering Department Seminar; also October 2006 at Cornell University Electrical Engineering Department Seminar and Tufts University Electrical Engineering Department Seminar.

May 2005, “High-speed serial links: Design Trends and Challenges” 17th Annual LEOS Workshop on Interconnections within High-Speed Digital Systems, Santa Fe, NM.

 
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