Journals and Magazines

1. Kim, B. and V. Stojanovic, “Modeling and Design Framework: Equalized and Repeated Interconnects for Networks-on-Chip [Invited],” to appear in IEEE Design & Test of Computers, 8 pages, 2008. (paper)
2. Barwicz, T., H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kärtner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects [Invited],” Journal of Optical Networking, vol. 6, no. 1, pp. 63-73, 2007. (paper)

Conferences

1. Kim, B. and V. Stojanovic, "A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmitter Filter and Transimpedance Receiver in 90nm CMOS Technology,"IEEE International Solid-State Circuit Conference, Feb. 2009. (paper).
2. Sredojevic, R. and V. Stojanovic, “Optimization-based Framework for Simultaneous Circuit and System Design-Space Exploration: A High-Speed Link Example,” to appear in IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 8 pages, November 2008. (paper)(talk)
3. Chen, F., H. Kam, D. Markovic, T.J. King, V. Stojanovic, and E. Alon, “Integrated Circuit Design with NEM Relays,” IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, 8 pages, November 2008. (paper)(talk)
4. Batten, C., A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic silicon photonics,” to appear in IEEE Symposium on High-Performance Interconnects, Stanford, CA, 10 pages, August 2008. (paper)(talk)
5. Blitvic, N. , L. Zheng, and V. Stojanovic ,”Low-complexity Pattern-eliminating Codes for ISI-limited Channels,” IEEE International Communications Conference, Beijing, China, 7 pages, pp. 1214-1219, May 2008. (paper)(talk)
6. Holzwarth, C. W., J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
7. Orcutt, J. S., A. Khilo, M. A. Popovic, C. W. Holzwarth, B. Moss, H. Li, M. S. Dahlem, T. D. Bonifield, F. X. Kärtner, E. P. Ippen, J. L. Hoyt, R. J. Ram, and V. Stojanovic, “Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
8. Kim, B. and V. Stojanovic, “Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework,” IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, pp. 552-559, November 2007.    (paper)(talk)
9. Chen, F., A. Joshi, V.Stojanovic, and A. Chandrakasan, “Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications,” ACM International Conference on Nano-Networks, Catania, Italy, p.8, September 2007.    (paper)(talk)
10. Blitvic, N. and V. Stojanovic, “Statistical Simulator for Block Coded Channels with Long Residual Interference,” IEEE International Conference on Communications, Glasgow, Scotland, pp. 6287-6294, June 2007. (paper)(talk)