Integrated Systems Group | Prof. Vladimir Stojanovic
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Integrated SySTEM DESIGN in Emerging Technologies

The overarching idea of this research theme is to develop circuit and system design techniques that best leverage the potential of the emerging switch and interconnect devices. This research both points to the potential impact of these new technolgies at the system/application level as well as sets the specifications and roadmaps that these new devices and technologies have to achieve to successfully compete and surpass the CMOS technology.

Integrated CMOS Photonics

Project Abstract
This project is investigating the integration of photonics in standard CMOS processes.  Multi-processor machines have become the norm, and the demand for high-bandwidth data links is increasing.  On-chip photonic systems have the potential to greatly increase link efficiency.  We are developing methods to integrate this exciting new technology from the transistor and circuit level through to the system architecture level, exploring the architecture and circuit implementation of photonic networks for core-to-core communication and memory systems.

People
Ben Moss, Michael Georgas, Jonathan Leu, Chen Sun in collaboration with research groups of Prof. Ram and Prof. Watts at MIT and Prof. Popovic at University of Colorado, Boulder and Prof. Asanovic at UC Berkeley

integrated circuit design using nano-electro-mechanical (NEM) switches

Project Abstract

Due to transistor leakage, CMOS circuits have a well-defined lower limit on their achievable energy efficiency. Once this limit is reached, power-constrained applications will face a cap on their maximum throughput independent of their level of parallelism.  This collaborative project proposes the use of nano/micro-electro-mechanical (N/MEM) switches to overcome the energy-efficiency limitations imposed by finite sub-thereshold slope in CMOS transistors. We are developing circuit, CAD, and device design methodologies for integrated circuit design using NEMS in order to demonstrate the applicability of this device technology.

People

MIT: Fred Chen, Hossein Fariborzi, Prof. Vladimir Stojanovic

UC-Berkeley: Matthew Spencer, Rhesa Nathanael, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Prof. Tsu-Jae King Liu, Prof. Elad Alon

UCLA: Chengcheng Wang, Kevin Dwan, Vaibhav Karkare, Prof. Dejan Markovic

PHOTONIC ADC

Project Abstract
Photonic analog-to-digital-converters have been gaining attention due to the need of high speed low jitter ADCs. State-of-art electrical ADCs are lagging behind the analog-to-digital conversion requirements of RF signals because of electrical jitter in the order of 100fs and non-linearity at very-high speed operation. As a result of the progress in laser technologies, optical lasers provide much lower jitter optical signals [1]. High-speed RF signals can be mapped on this pulse and can be demultiplexed into N channels by filtering where the frequency intervals linearly maps to time intervals. After post processing these signals at a frequency of f, N*f sampling frequency can be achieved by multiplexing the channels back [2]. So, a 20GHz signal can be demultiplexed into 20 channels and each channel can be converted to digital domain at 1GHz [3].

People
O. Uyar, A. Khilo , J. S. Orcutt , C. Sorace, B. Moss, A. Nejadmalayeri

 

Integrated SySTEM DESIGN in DEEP Sub-MICRON CMOS

The overaching idea of this research theme is the tight interaction of the communication system algorithms and their implementation in the light of tight energy-constraints across a range of integrated communication systems applications - from wireless sensor nodes to high-throughput, power-constrained mm-wave radios and wireline backplanes, servers and manycore memory systems.

NONLINEAR MODELING and COMPENSATION ARCHITECTURES FOR ANALOG FRONT-ENDS

Project Abstract
In this project we are developing design and modeling methodologies for identification and compensation of analog front-end nonlinearities in deep sub-micron processes. Examples include nonlinear modeling and VLSI compensation architectures for mm-wave Power Amplifiers, impedance modulating energy-efficient high-speed link transmit equalizers/drivers, and other analog components. Of particular interest are compensation architectures that operate at high-throughputs (e.g. mm-wave baseband units and high-speed link circuits), where traditional digital signal processing techniques perform poorly.

People
Yan Li, Ranko Sredojevic, Zhipeng Li and Oguzhan Uyar,

in collaboration with Prof. Megretski and Prof. Dawson's research group at MIT and Prof. Rickets' research group at CMU

hardware efficient algorithms and circuit architectures for wireless sensor applications

Project Abstract
There are a number of wireless sensor applications ranging from environmental monitoring to medical implants. In almost all of these applications, the utility of the wireless sensor node is limited by its finite energy source and the replacement cost of the node once the source has been exhausted. In this work, we examine this problem from the perspective of the sensor node's energy consumption and explore algorithms and circuit architectures that might significantly improve on the energy-efficiency of wireless sensor nodes and hence extend their utility.In particular we explore the adoption of a system architecture based on compressed sensing and look at how to realize a hardware efficient implementation.

People
Fred Chen, Fabian Lim

DESIGN oF ERROR-CORRECTION SYSTEMS for ENERGY-CONSTRAINED COMMUNICATION SYSTEMS

Project Abstract
This project explores the interactions of coding algorithms and VLSI implementations under energy-constrained conditions, studying the optimal power allocation on all the blocks in the transmission system (PA - transmitter, and decoder - receiver).

 

People
Wei An, Fabian Lim in collaboration with Prof. Kavcic at University of Hawaii at Manoa.

Circuit and System Techniques for On-Chip Interconnects

Project Abstract
By introducing equalization into VLSI on-chip signaling environments, we plan to improve both data rate and energy-efficiency of bandlimited long interconnects in a network on-a-chip (NoC) of a chip-multi-processor. As the number of cores increases, the efficiency of a NoC becomes a critical design issue. Equalization can improve both data rate and energy costs for a given utilization of metal resources when compared to repeater insertion techniques. To enable the design of equalized interconnects, we developed a model and tool for fast design space exploration to get trade-off curves when many wire, circuit, and link parameters are optimized. Currently, we are leveraging the results of this optimization framework in developement of novel circuit techniques for on-chip link transceivers.

People
Chen Sun, Byungsub Kim

 

PAST PROJECTS

Convex Optimization of Integrated Communications Systems

Project Abstract
The project aims to build a framework for fast and efficient design of integrated communication systems. By using convex optimization to optimize underlying heterogeneous circuit blocks and obtain their trade-off functions, the aim is to further develop the methodology to piece these trade-off functions into a simplified description of the whole system design space. This makes the job of a system designer straightforward and breaks the traditional iterative design process. We do not seek to replace designers with a complex synthesis tool. Rather, we advance convex optimization as a powerful extension of a designer’s analytical capability, one that will make the system design problem as tractable as the circuit block design problem currently is. Our work will greatly reduce the time it takes to design many types of modern communication systems.

People
Ranko Sredojevic, Yan Li, Tania Khanna, Prof. Joel Dawson

Channel-and-Circuits-Aware, Energy-Efficient Coding for High-Speed Links

Project Abstract
In this project we aim to extend the link system design to incorporate energy-efficient coding techniques. Using novel energy-efficient coding techniques for non-Gaussian noise and residual interference, we seek to increase both the achievable data rates and the energy-efficiency of links by drastically off-loading the low-BER target burden and hence decreasing the complexity of the equalization/modulation level. This project not only involves design of new coding techniques but also novel link modeling and simulation methods to accurately predict the performance of different coding techniques.

The three current areas of research in coding for high-speed links are:

People
Natasa Blitvic, Maxine Lee, Prof. Lizhong Zheng.

 

Unified System and Circuit Design of High-Speed Serial Links

Project Abstract
To extend the reach and improve the energy-efficiency of today’s high-speed electrical links, we need to approach their design from a bandlimited communications system standpoint, while preserving the intricate understanding of the issues that constrain the high-speed link circuit design. In this project, we are investigating the most appropriate communication scheme for the high-speed link environment by combining new algorithms with novel, fast, high-precision and low-noise circuits.

People
Sanquan Song

 

Evaluation and characterization of carbon nanotube interconnects for vlsi applications

Project Abstract
As CMOS processes scale into the nanometer regime, lithography limitations, electromigration and the increasing resistivity and relative delay of copper interconnects has driven the need to find alternative interconnect solutions.  Carbon nanotubes (CNT) have emerged as a potential candidate to replace copper interconnects because of their ballistic transport and ability to carry large current densities in the absence of electromigration.  The goal of this project is to address the need to connect the impact of emerging interconnect technologies, such as carbon nanotubes, to the system applications they will ultimately be used for.

People
Fred Chen

 

RLE Progress Reports

  1. PR 147, 2004-2005, Integrated Systems (PDF Format)

MTL Reports

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