Project Abstract
By introducing equalization into VLSI on-chip signaling environments, we plan to improve both data rate and energy-efficiency of bandlimited long interconnects in a network on-a-chip (NoC) of a chip-multi-processor. As the number of cores increases, the efficiency of a NoC becomes a critical design issue. Equalization can improve both data rate and energy costs for a given utilization of metal resources when compared to repeater insertion techniques. To enable the design of equalized interconnects, we developed a model and tool for fast design space exploration to get trade-off curves when many wire, circuit, and link parameters are optimized. Currently, we are leveraging the results of this optimization framework in developement of novel circuit techniques for on-chip link transceivers.
People
Byungsub Kim
Project Abstract
The project aims to build a framework for fast and efficient design of integrated
communication systems. By using convex optimization to optimize underlying
heterogeneous circuit blocks and obtain their trade-off functions, the
aim is to further develop the methodology to piece these trade-off functions
into a simplified description of the whole system design space. This makes
the job of a system designer straightforward and breaks the traditional
iterative design process. We do not seek to replace designers with a complex
synthesis tool. Rather, we advance convex optimization as a powerful extension
of a designer’s analytical capability, one that will make the system
design problem as tractable as the circuit block design problem currently
is. Our work will greatly reduce the time it takes to design many types
of modern communication systems.
People
Ranko Sredojevic, Yan Li, Tania Khanna, Prof. Joel Dawson
Project
Abstract
In this project we aim to extend the link system design to incorporate
energy-efficient coding techniques. Using novel energy-efficient
coding techniques for non-Gaussian noise and residual interference,
we seek to increase both the achievable data rates and the energy-efficiency
of links by drastically off-loading the low-BER target burden
and hence decreasing the complexity of the equalization/modulation
level. This project not only involves design of new coding techniques
but also novel link modeling and simulation methods to accurately
predict the performance of different coding techniques.
The
three current areas of research in coding for high-speed links
are:
People
Natasa Blitvic, Maxine Lee, Prof. Lizhong Zheng.
Project Abstract
To extend the reach and improve the energy-efficiency of today’s high-speed
electrical links, we need to approach their design from a bandlimited communications
system standpoint, while preserving the intricate understanding of the issues
that constrain the high-speed link circuit design. In this project, we are
investigating the most appropriate communication scheme for the high-speed
link environment by combining new algorithms with novel, fast, high-precision
and low-noise circuits.
People
Sanquan Song
Project
Abstract
As CMOS processes scale into the nanometer regime, lithography
limitations, electromigration and the increasing resistivity and
relative delay of copper interconnects has driven the need to
find alternative interconnect solutions. Carbon nanotubes
(CNT) have emerged as a potential candidate to replace copper
interconnects because of their ballistic transport and ability
to carry large current densities in the absence of electromigration.
The goal of this project is to address the need to connect the
impact of emerging interconnect technologies, such as carbon nanotubes,
to the system applications they will ultimately be used for.
People
Fred Chen
Project
Abstract
This project is investigating the integration of photonics in
standard CMOS processes. Multi-processor machines have become
the norm, and the demand for high-bandwidth data links is increasing.
On-chip photonic systems have the potential to greatly increase
link efficiency. We are developing methods to integrate
this exciting new technology from the transistor and circuit level
through to the system architecture level.
People
Ajay Joshi, Ben Moss, Michael Georgas, Jonathan Leu
- PR
147, 2004-2005, Integrated Systems (PDF Format)
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