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Sponsors

Lincoln Laboratories, Advanced Concepts Committee, SRC/FCRP C2S2

People

Ranko Sredojevic, Yan Li, Tania Khanna, Professor Vladimir Stojanovic and Professor Joel Dawson

Many integrated communication systems today are constrained by either throughput or power dissipation. Cases from high-speed I/O interfaces in processors and routers to low-power radios in cell phones and sensors force designers to tackle one of the two dual problems – optimizing the overall data rate with given power constraints or minimizing the power for given throughput. While much work has gone into both the circuit and communications sides of the problem, the hardest part seems to be communicating the requirements/costs and characteristics of circuits and components to the algorithm level and vice versa, so that the overall optimum can occur. Many design hours and iterations on the system architectures are needed before a system is designed and even then very little data exists on the scope of design space or the cost/performance space of the implemented components. What is the new optimal system if the specifications change slightly? To solve these problems, we intend to use the convex optimization as a framework to connect the circuit and system design abstractions.

We are developing a design-optimization framework in which an integrated communication system is constructed out of pre-characterized macros of analog, digital and mixed-signal circuits. Through the use of convex optimization, tradeoff functions and defined regions of operation are found for each macro. This information is then used at a higher–system design level to determine the right blend of algorithms and system architecture that implement a globally efficient communication system. This process is depicted in Fig. 1, on an example radio system. Convex optimization is critical to this effort, since it also provides the sensitivities of each objective function of the underlying circuit/block parameters, which builds intuition about the design and guides the designer in making intelligent topology changes. This challenging work is currently considered akin to black magic since the problem in general is combinatorial and NP-hard.

We intend to follow the work in [1]-[3] by putting their effort into a more general framework. We are currently building our own integrated circuit optimization flow. This will allow us not only to optimize a given circuit architecture, but also to explore different architectures, finding the ones that lend themselves nicely to convex optimization. We are currently working on a library of these adjustable or optimizable macros, such as mixers, VCOs, amplifiers, ADCs, DACs, and even their building elements. With this base and initial optimization results for each of the macros, we intend to engage in a system-level optimization on two example systems:  a narrowband communication system (for example, a cell phone radio or a sensor) and a wideband communication system (an ultra-wideband radio or a multi-Gb/s high-speed chip-to-chip link [4],[5]).

• Robust Optimization for Analog Integrated Circuits

As the technology node scales down into deep submicron regime, analog circuits become more and more vulnerable to process variations and manufacture yields go down rapidly. We are developing and incorporating a robust circuit design methodology into the framework of equation-based circuit design [1]-[3], with which we are able to generate robust trade-off surfaces for hierarchical system design. Process variations such as threshold voltage, current mismatch and etc. are captured and modeled into the optimization problem, which characterizes the circuit with the impact of variations. The resulted design then meets all specs under those variations taken into account. An iterative robust optimization algorithm which mimics the monte-carlo check is under development. We are also planning on looking into the problems with larger scale of variations.   

Figure 1: System-level partitioning: Underlying blocks optimized using convex optimization are described at the system level through the corresponding trade-off functions.

References

1. M. M. Hershenson, "Efficient Description of the Design Space of Analog Circuits," Design Automation Conference, pp. 970-973, 2003.
2. M. M. Hershenson, "Design of Pipeline Analog-to-digital Converters via Geometric Programming," ICCAD 2002, pp. 317-324.
3. D. M. Colleran, et al. "Optimization of Phase-locked Loop Circuits via Geometric Programming," IEEE Custom Integrated Circuits Conference, pp. 377-380, 2003.
4. V. Stojanovic, A. Amirkhany, M. Horowitz, "Optimal Linear Precoding with Theoretical and Practical Data Rates in High-Speed Serial-Link Backplane Communication," IEEE International Conference on Communications, pp. 2799-2806, June 2004.
5. V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, E. Alon, C. Werner, J. Zerbe, M.A. Horowitz, "Adaptive Equalization and Data Recovery in a Dual-mode (PAM2/4) Serial Link Transceiver," IEEE Symposium on VLSI Circuits, June 2004, pp. 348-351.