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Unified System and Circuit Design of High-speed Serial Links Sponsors National Semiconductor People Sanquan Song and Professor Vladimir Stojanovic To reach the energy-efficiency and rate limits of high-speed serial links, we need to design the circuits with deep understanding of the bandwidth limited communication systems. In this project, we want to first find the most appropriate communication scheme for the high-speed serial link environment and implement it with novel circuits. Communication techniques, such as modulation and equalizations, have been applied to the state-of-the-art high-speed links and increase the date rate to 6-10Gbps over a variety of 3-30" backplane channels. A simple calculation shows that such rate is far away from the Shannon capacity of these channels. We want to apply advanced communication techniques, such as modern modulation methods and optimized equalizer, to narrow this gap. Given that these high-speed link transceivers are densely integrated into power-limited chips, the power efficiency of these transceivers is very critical to the system. Starting from the channel properties and noise sources, we want to treat the link as a bandwidth-limited power-limited communication system and develop a novel communication scheme to integrate the modulation techniques, equalizers and CDR methods so that it works with a higher data rate, lower power consumption and can operate over a variety of channels.
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