Energy-Efficient
Multimedia Systems Group

Professor Vivienne Sze

Principal Investigator: Vivienne Sze

Sze_bio

Degrees

  • Ph.D. in Electrical Engineering, MIT, 2010
  • S.M. in Electrical Engineering, MIT, 2006
  • B.A.Sc. (Hons) in Electrical Engineering, University of Toronto, 2004

Teaching

  • 6.812/6.825 (formerly 6.S082/6.888) Hardware Architecture for Deep Learning, Fall 2017, Spring 2019, Spring 2020
  • 6.344 Digital Image Processing, Spring 2014, Spring 2017
  • 6.374 Analysis and Design of Digital Integrated Circuits, Fall 2013 – 2016, 2018, 2019, 2020
  • 6.003 Signals and Systems, Spring 2018
  • 6.01 Intro to EECS I, Spring 2015
  • MIT Professional Education Short Course on Designing Efficient Deep Learning Systems

Awards and Fellowships

  • 2020 ACM-W Rising Star Award [ Video ]
    For contributions to the development of new techniques that bridge algorithm and hardware design, enabling optimization across multiple layers of abstraction for greatly improved performance
  • 2019 Edgerton Faculty Award
  • 2018 Symposium on VLSI Circuits Best Student Paper Award
    for “Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones”
  • 2018 Google Faculty Research Award
  • 2018 Facebook Faculty Award
  • 2018 Qualcomm Faculty Award
  • 2017 CICC Outstanding Invited Paper Award
    for “Hardware for Machine Learning: Challenges and Opportunities”
  • 2017 Qualcomm Faculty Award
  • Member of the JCT-VC team that received the 2017 Primetime Engineering Emmy Award for the development of the HEVC video compression standard
  • 2016 Google Faculty Research Award
  • 2016 IEEE Micro Top Picks in Computer Architecture
    for “Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks”
  • 2016 AFOSR Young Investigator Research Program (YIP) Award
  • 2016 3M Non-Tenured Faculty Award
  • 2014 DARPA Young Faculty Award (YFA)
  • 2011 Jin-Au Kong Outstanding Doctoral Thesis Prize in electrical engineering at MIT
    for “Parallel algorithms and architectures for low power video decoding”
  • 2008 A-SSCC Outstanding Design Award
  • 2007 DAC/ISSCC Student Design Contest Award
  • Texas Instruments Graduate Women’s Fellowship for Leadership in Microelectronics in 2008
  • Natural Sciences and Engineering Research Council of Canada (NSERC) Postgraduate Scholarships in 2005 and 2007
  • Natural Sciences and Engineering Research Council of Canada (NSERC) Julie Payette Fellowship in 2004
  • University of Toronto Adel S. Sedra Gold Medal, Henry G. Acres Medal and W.S. Wilson Medal in 2004

Professional Activities

  • Technical Program Committee (Machine Learning and AI sub-committee), International Solid-State Circuits Conference (ISSCC) (2020 – present)
  • (Systems) Program Chair, Machine Learning and Systems (MLSys) Conference (2020)
  • Technical Program Committee, Symposium on VLSI Circuits (2016 – 2019)
  • Program Committee, Machine Learning and Systems (MLSys) Conference (2019)
  • Advisory Committee (AdCom), IEEE Solid-State Circuit Society (SSCS) (2018 – 2020)
  • Distinguished Lecturer, IEEE Solid-State Circuit Society (SSCS) (2018 – 2019)
  • Program Committee, IEEE/ACM International Symposium on Microarchitecture (MICRO) (2017, 2018)
  • Chair for workshop on “Circuits for Social Good” at 2018 International Solid-State Circuits Conferences (ISSCC)
  • Guest Editor for special issue on “Efficient HEVC Implementations” in IEEE Transactions on Circuits and Systems for Video Technology (TCSVT)
  • Elected Member of the IEEE Signal Processing Society’s Image, Video, and Multidimensional Signal Processing Technical Committee (IVMSP TC) (2014 – 2016)
  • Elected Member of the IEEE Signal Processing Society’s Design and Implementation of Signal Processing Systems Technical Committee (DISPS TC) (2014 – 2016)