Energy-Efficient
Multimedia Systems Group
Professor Vivienne Sze

Publications

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* Indicates authors contributed equally to the work

2023

  • Z. Y. Xue, Y. N. Wu, J. S. Emer, V. Sze, “Tailor Swiftiles: Accelerating Sparse Tensor Algebra by Overbooking Buffer Occupancy,” to appear at ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct 2023.
  • Y. N. Wu, P.-A. Tsai, S. Muralidharan, A. Parashar, V. Sze, J. S. Emer, “HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity,” to appear at ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct 2023. [ paper arXiv ]
  • P. Z. X. Li, S. Karaman, V. Sze, “GMMap: Memory-Efficient Continuous Occupancy Map Using Gaussian Mixture Model,” arXiv, June 2023. [ paper arXiv ]
  • T. Andrulis, J. Emer, V. Sze, “RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!,” International Symposium on Computer Architecture (ISCA), June 2023. [ paper PDF | lightning talk video | code github ]
  • V. Sivaraman, P. Karimi, V. Venkatapathy, M.Khani, S. Fouladi, M. Alizadeh, F. Durand, V. Sze, “Gemino: Practical and Robust Neural Compression for Video Conferencing,” to appear at USENIX Symposium on Networked Systems Design and Implementation (NDSI) [ paper arXiv ]
  • M. Gilbert, Y. N. Wu, A. Parashar, V. Sze, J. Emer, “LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators,” IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2023. [ PDF ]
  • H.-Y. Lai, C. Sodini, V. Sze, T. Heldt, “Individualized Tracking of Neurocognitive-State-Dependent Eye-Movement Features Using Mobile Devices,” Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies (IMWUT), Vol. 7, No. 1, pp. 1 – 23, March 2023. [ LINK ]
  • S. Sudhakar, V. Sze, S. Karaman, “Data Centers on Wheels: Emissions from Computing Onboard Autonomous Vehicles,” IEEE Micro, Special Issue on Environmentally Sustainable Computing, Vol. 43, No. 1, pp. 29 – 39, January/February 2023. [ paper PDF | slides PDF | TEDx talk video | Technical talk video ] Highlighted in MIT News and The Washington Post

2022

  • Y. N. Wu, P. Tsai, A. Parashar, V. Sze, J. Emer, “Sparseloop: An Analytical Approach to Sparse Tensor Accelerator Modeling,” ACM/IEEE International Symposium on Microarchitecture (MICRO), October 2022. [ paper PDF | video LINK | project website LINK | code github ] MICRO 2022 Distinguished Artifact Award
  • S. Sudhakar, S. Karaman, V. Sze, “Carbon Emissions from Computing Onboard Autonomous Vehicles,” ICRA 2022 Workshop on Robotics for Climate Change, May 2022.
  • P. Z. X. Li, S. Karaman, V. Sze, “Memory-Efficient Gaussian Fitting for Depth Images in Real Time,” IEEE International Conference on Robotics and Automation (ICRA), May 2022. [ paper PDF | video LINK ]
  • S. Sudhakar, V. Sze, S. Karaman, “Uncertainty from Motion for DNN Monocular Depth Estimation,” IEEE International Conference on Robotics and Automation (ICRA), May 2022. [ paper PDF | video LINK ]
  • H.-Y. Lai, G. Saavedra-Pena, C. G. Sodini, T. Heldt, V. Sze, “App-based saccade latency and directional error determination across the adult age spectrum,” IEEE Transactions on Biomedical Engineering (TBME), Vol. 69, No. 2, pp. 1029 – 1039, February 2022. [ PDF ]

2021

  • Y.-L. Liao, S. Karaman, V. Sze, “Searching for Efficient Multi-Stage Vision Transformers,” ICCV 2021 Workshop on Neural Architectures: Past, Present and Future, October 2021. [ paper arXiv | code github ]
  • K. Gupta, P. Z. X. Li, S. Karaman, V. Sze, “Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time,” IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), September 2021. [ PDF ]
  • T.-J. Yang, Y.-L. Liao, V. Sze, “NetAdaptV2: Efficient neural architecture search with fast super-network training and architecture optimization,” IEEE Conference on Computer Vision and Pattern Recognition (CVPR), June 2021. [ paper PDF | poster PDF | slides PDF | project website LINK ]
  • F. Wang, Y. N. Wu, M. Woicik, J. S. Emer, V. Sze, “Architecture-Level Energy Estimation for Heterogeneous Computing Systems,” IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021. [ paper PDF | code github ]
  • Y. N. Wu, P.-A. Tsai, A. Parashar, V. Sze, J. S. Emer, “Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators,” IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021. [ paper PDF | tutorial website LINK ]
  • L. Bernstein, A. Sludds, R. Hamerly, V. Sze, J. Emer, D. Englund, “Freely scalable and reconfigurable optical hardware for deep learning,” Scientific Reports, Vol. 11, No. 3144, February 2021. [ LINK ]

2020

  • V. Sze, Y.-H. Chen, T.-Y. Yang, J. S. Emer, “How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful,” IEEE Solid-State Circuits Magazine, Vol. 12, No. 3, pp. 28-41, Summer 2020. [ PDF ]
  • Z. Zhang, T. Henderson, S. Karaman, V. Sze, “FSMI: Fast computation of Shannon Mutual Information for information-theoretic mapping,” International Journal of Robotics Research (IJRR), Vol. 39, No. 9, pp. 1155-1177, August 2020. [ PDF ]
  • J. Noraky, V. Sze, “Low Power Depth Estimation of Rigid Objects for Time-of-Flight Imaging,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), Vol. 30, No. 6, pp. 1524-1534, June 2020. [ PDF ]
  • S. Sudhakar, S. Karaman, V. Sze, “Balancing Actuation and Computing Energy in Motion Planning,” IEEE International Conference on Robotics and Automation (ICRA), May 2020. [ PDF | video LINK ]
  • T. Henderson, V. Sze, S. Karaman, “An Efficient and Continuous Approach to Information-Theoretic Exploration,” IEEE International Conference on Robotics and Automation (ICRA), May 2020. [ paper PDF | video LINK ] Based on thesis that received First Place for the 2020 David Adler Memorial Thesis Award
  • Y. N. Wu, V. Sze, J. S. Emer, “An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs,” IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2020. [ paper PDF | code github ]
  • H.-Y. Lai, G. Saavedra Peña, C. Sodini, V. Sze, T. Heldt, “Measuring Saccade Latency Using Smartphone Cameras,” IEEE Journal of Biomedical and Health Informatics (JBHI), Vol. 24, No. 3, pp. 885-897, March 2020. [ PDF ]
  • J. Noraky, V. Sze, “Depth Map Estimation of Dynamic Scenes Using Prior Depth Information,” arXiv, February 2020. [ paper arXiv ]

2019

  • T.-J. Yang, V. Sze, “Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators,” IEEE International Electron Devices Meeting (IEDM), Invited Paper, December 2019. [ paper PDF | slides PDF ]
  • Y. N. Wu, J. S. Emer, V. Sze, “Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs,” International Conference on Computer Aided Design (ICCAD), November 2019. [ paper PDF | slides PDF | project website LINK | code github ]
  • J. Noraky, C. Mathy, A. Cheng, V. Sze, “Low Power Adaptive Time-Of-Flight Imaging For Multiple Rigid Objects,” IEEE International Conference on Image Processing (ICIP), September 2019. [ PDF ]
  • P. Z. X. Li*, Z. Zhang*, S. Karaman, V. Sze, “High-throughput Computation of Shannon Mutual Information on Chip,” Robotics: Science and Systems (RSS), June 2019. [ paper PDF | poster PDF | slides PDF | video LINK | supplementary material PDF ] Extension of this work received First Place at the 2020 ACM Student Research Competition Grand Finals
  • Y.-H. Chen, T.-J Yang, J. Emer, V. Sze, “Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 9, No. 2, pp. 292-308, June 2019. [ paper PDF | extended version arXiv ]
  • Z. Zhang, T. Henderson, V. Sze, S. Karaman, “FSMI: Fast computation of Shannon Mutual Information for information-theoretic mapping,” IEEE International Conference on Robotics and Automation (ICRA), May 2019. [ paper PDF | poster PDF | summary video | extended preprint arXiv ]
  • D. Wofk*, F. Ma*, T.-J. Yang, S. Karaman, V. Sze, “FastDepth: Fast Monocular Depth Estimation on Embedded Systems,” IEEE International Conference on Robotics and Automation (ICRA), May 2019. [ paper PDF | poster PDF | project website LINK | summary video | code github ] Received SuperUROP Award
  • A. Suleiman, Z. Zhang, L. Carlone, S. Karaman, V. Sze, “Navion: A 2mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones,” IEEE Journal of Solid-State Circuits (JSSC), VLSI Symposia Special Issue, Vol. 54, No. 4, pp. 1106-1119, April 2019. [ paper PDF | project website LINK ]
  • T.-J. Yang, M. D. Collins, Y. Zhu, J.-J. Hwang, T. Liu, X. Zhang, V. Sze, G. Papandreou, L.-C. Chen, “DeeperLab: Single-Shot Image Parser,” arXiv, February 2019. [ paper arXiv | project website LINK ]

2018

  • J. Noraky, V. Sze, “Depth Estimation of Non-Rigid Objects For Time-Of-Flight Imaging,” IEEE International Conference on Image Processing (ICIP), October 2018. [ paper PDF | poster PDF ]
  • H.-Y. Lai, G. Saavedra Peña, C. Sodini, T. Heldt, V. Sze, “Enabling Saccade Latency Measurements with Consumer-Grade Cameras,” IEEE International Conference on Image Processing (ICIP), October 2018. [ paper PDF | poster PDF ]
  • T.-J. Yang, A. Howard, B. Chen, X. Zhang, A. Go, M. Sandler, V. Sze, H. Adam, “NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications,” European Conference on Computer Vision (ECCV), September 2018. [ paper arXiv | poster PDF | project website LINK | code github ]
  • M. Tikekar, V. Sze, A. P. Chandrakasan, “A Fully-Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 8, pp. 2368-2377, August 2018. [ PDF ]
  • G. Saavedra Peña, H.-Y. Lai, V. Sze, T. Heldt, “Determination of saccade latency distributions using video recordings from consumer-grade devices,” IEEE International Engineering in Medicine and Biology Conference (EMBC), July 2018. [ paper PDF | poster PDF ]
  • A. Suleiman, Z. Zhang, L. Carlone, S. Karaman, V. Sze, “Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones,” IEEE Symposium on VLSI Circuits (VLSI-Circuits), June 2018. [ paper PDF | slides PDF | poster PDF | project website LINK ] Featured as a technical highlight at the conference, highlighted in MIT News, and received Best Student Paper Award
  • Y.-H. Chen*, T.-J. Yang*, J. Emer, V. Sze, “Understanding the Limitations of Existing Energy-Efficient Design Approaches for Deep Neural Networks,” SysML Conference, February 2018. [ paper PDF | talk video ] Selected for Oral Presentation

2017

  • V. Sze, Y.-H. Chen, T.-J. Yang, J. Emer, “Efficient Processing of Deep Neural Networks: A Tutorial and Survey,” Proceedings of the IEEE, vol. 105, no. 12, pp. 2295-2329, December 2017. [ PDF | earlier version arXiv ] Cover Article in Proceedings of the IEEE
  • V. Sze, “Designing Hardware for Machine Learning: The Important Role Played by Circuit Designers,” IEEE Solid-State Circuits Magazine, vol. 9, no. 4, pp. 46-54, Fall 2017. [ LINK ]
  • T.-J. Yang, Y.-H. Chen, J. Emer, V. Sze, “A Method to Estimate the Energy Consumption of Deep Neural Networks,” Asilomar Conference on Signals, Systems and Computers, Invited Paper, October 2017. [ paper PDF | slides PDF ]
  • J. Noraky, V. Sze, “Low Power Depth Estimation for Time-of-Flight Imaging,” IEEE International Conference on Image Processing (ICIP), September 2017. [ paper PDF | poster PDF ]
  • T.-J. Yang, Y.-H. Chen, V. Sze, “Designing Energy-Efficient Convolutional Neural Networks
    using Energy-Aware Pruning,” IEEE Conference on Computer Vision and Pattern Recognition (CVPR), July 2017. [ paper arXiv | poster PDF | DNN energy estimation tool LINK | DNN models LINK ] Highlighted in MIT News
  • Z. Zhang, V. Sze, “FAST: A Framework to Accelerate Super-Resolution Processing on Compressed Videos,” CVPR Workshop on New Trends in Image Restoration and Enhancement, July 2017. [ paper PDF | slides PDF | poster PDF | code ZIP | earlier version arXiv | project website LINK ]
  • Z. Zhang*, A. Suleiman*, L. Carlone, V. Sze, S. Karaman, “Visual-Inertial Odometry on Chip: An Algorithm-and-Hardware Co-design Approach,” Robotics: Science and Systems (RSS), July 2017. [ paper PDF | slides PDF | poster PDF | supplementary material PDF | project website LINK ] Highlighted in MIT News
  • M. Tikekar, V. Sze, A. Chandrakasan, “A Fully-Integrated Energy-Efficient H.265/HEVC Decoder with eDRAM for Wearable Devices,” IEEE Symposium on VLSI Circuits (VLSI-Circuits), June 2017. [ paper PDF | slides PDF ]
  • Y.-H. Chen, J. Emer, V. Sze, “Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators,” IEEE Micro’s Top Picks from the Computer Architecture Conferences, Vol. 37, No. 3, pp. 12-21, May/June 2017. [ PDF ] IEEE MICRO Top 25 Most Downloaded (June 2017 – May 2018)
  • A. Suleiman*, Y.-H. Chen*, J. Emer, V. Sze, “Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision,” IEEE International Symposium of Circuits and Systems (ISCAS), Invited Paper, May 2017. [ paper PDF | slides PDF | talk video ]
  • V. Sze, Y.-H. Chen, J. Emer, A. Suleiman, Z. Zhang, “Hardware for Machine Learning: Challenges and Opportunities,” IEEE Custom Integrated Circuits Conference (CICC), Invited Paper, May 2017. [ paper arXiv | slides PDF ] Received Outstanding Invited Paper Award
  • A. Suleiman, Z. Zhang, V. Sze, “A 58.6mW 30fps Real-Time Programmable Multi-Object Detection Accelerator with Deformable Parts Models on Full HD 1920×1080 Videos,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 3, pp. 844-855, March 2017. [ PDF ]
  • Y.-H. Chen, T. Krishna, J. Emer, V. Sze, “Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,” IEEE Journal of Solid-State Circuits (JSSC), ISSCC Special Issue, Vol. 52, No. 1, pp. 127-138, January 2017. [ paper PDF | project website LINK ] Top 5 most cited JSSC paper of all time

2016

  • Y.-H. Chen, J. Emer, V. Sze, “Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks,” International Symposium on Computer Architecture (ISCA), pp. 367-379, June 2016. [ paper PDF | slides PDF ] Selected for IEEE Micro’s Top Picks special issue on “most significant papers in computer architecture based on novelty and long-term impact” from 2016
  • A. Suleiman, Z. Zhang, V. Sze, “A 58.6mW Real-time Programmable Object Detection with Multi-Scale Multi-Object Support Using Deformable Parts Models on 1920×1080 Video at 30fps,” IEEE Symposium on VLSI Circuits (VLSI-Circuits), pp. 184-185, June 2016. [ paper PDF | slides PDF ]
  • Y.-H. Chen, T. Krishna, J. Emer, V. Sze, “Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,” IEEE International Conference on Solid-State Circuits (ISSCC), pp. 262-264, February 2016. [ paper PDF | slides PDF | poster PDF | demo video | project website LINK ] Highlighted in EETimes and MIT News, and Top 3 most cited ISSCC paper of all time

2015

  • A. Suleiman, V. Sze, “An Energy-efficient Hardware Implementation of HOG-based Object Detection at 1080HD 60 fps with Multi-scale Support,” Journal of Signal Processing Systems, SiPS Special Issue, December 2015. [ PDF ]
  • Z. Zhang, V. Sze, “Rotate Intra Block Copy for Still Image Coding,” IEEE International Conference on Image Processing (ICIP), September 2015. [ paper PDF | poster PDF ]
  • Y.-H. Chen, V. Sze, “A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), Vol. 25, No. 5, pp. 856-868, May 2015. [ PDF ]

2014

  • A. Suleiman, V. Sze, “Energy-Efficient HOG-based Object Detection at 1080HD 60 fps with Multi-Scale Support,” IEEE International Workshop on Signal Processing Systems (SiPS), pp. 256-261, October 2014. [ paper PDF | slides PDF ]
  • Y.-H. Chen, V. Sze, “A 2014 Mbin/s Deeply Pipelined CABAC Decoder For HEVC,” IEEE International Conference on Image Processing (ICIP), pp. 2110-2114, October 2014. [ paper PDF | slides PDF ]
  • M. Tikekar, C.-T. Huang, V. Sze, A. Chandrakasan, “Energy and Area-Efficient Hardware Implementation of HEVC Inverse Transform and Dequantization,” IEEE International Conference on Image Processing (ICIP), pp. 2100-2104, October 2014. [ paper PDF | slides PDF ] Top 10% Paper Recognition at ICIP
  • M. Tikekar, C.-T. Huang, C. Juvekar, V. Sze, A. P. Chandrakasan, “A 249 MPixel/s HEVC Video-Decoder Chip for 4K Ultra HD Applications,” IEEE Journal of Solid-State Circuits (JSSC), ISSCC Special Issue, Vol. 49, No. 1, pp. 61-72, January 2014. [ PDF ]

2013

  • M. E. Sinangil, V. Sze, M. Zhou, A. P. Chandrakasan, “Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard,” IEEE Journal of Selected Topics in Signal Processing, Vol. 7, No.6, pp. 1017-1028, December 2013. [ PDF ] J-STSP Top 25 Most Downloaded (Oct 2013 – March 2014)
  • M. Budagavi, A. Fuldseth, G. Bjontegaard, V. Sze, M. Sadafale, “Core Transform Design in the High Efficiency Video Coding (HEVC) Standard,” IEEE Journal of Selected Topics in Signal Processing, Vol.7, No. 6, pp. 1029-1041, December 2013. [ PDF ] J-STSP Top 25 Most Downloaded (Aug 2013 – Aug 2014)
  • V. Sze, M. Budagavi, “A Comparison of CABAC Throughput for HEVC/H.265 vs. AVC/H.264,” IEEE Workshop on Signal Processing Systems (SiPS), pp. 165-170, October 2013. [ PDF ]
  • C.-T. Huang, M. Tikekar, C. Juvekar, V. Sze, A. P. Chandrakasan, “A 249Mpixels/s HEVC Video Decoder Chip for Quad Full HD Applications,” IEEE International Conference on Solid-State Circuits (ISSCC), pp. 162-163, February 2013. [ PDF ] Highlighted in MIT News

2012

  • V. Sze, M. Budagavi, “High Throughput CABAC Entropy Coding in HEVC,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), Vol. 22, No. 12, pp. 1778-1791, December 2012. [ PDF ] TCSVT Top 25 Most Downloaded (June 2013, Aug 2013, Nov 2013, April 2014)
  • M. E. Sinangil, V. Sze, M. Zhou, A. P. Chandrakasan, “Memory cost vs. Coding efficiency trade-offs for HEVC motion estimation engine,” IEEE International Conference on Image Processing (ICIP), pp. 1533-1536, September 2012. [ PDF ]
  • M. E. Sinangil, V. Sze, M. Zhou, A. P. Chandrakasan, “Hardware-aware motion estimation search algorithm development for High-Efficiency Video Coding (HEVC) standard,” IEEE International Conference on Image Processing (ICIP), pp. 1529-1532, September 2012. [ PDF ]
  • M. Budagavi, V. Sze, “Unified forward+inverse transform architecture for HEVC,” IEEE International Conference on Image Processing (ICIP), pp. 209-212, September 2012. [ PDF ]
  • M. Zhou, V. Sze, M. Budagavi, “Parallel Tools in HEVC for High-Throughput Processing,” SPIE Optical Engineering + Applications, Applications of Image Processing XXXV, August 2012. [ PDF ]
  • V. Sze, M. Budagavi, “Parallelization of Transform Coefficient Coding for HEVC,” IEEE Picture Coding Symposium (PCS), pp. 509 – 512, May 2012. [ PDF ]
  • V. Sze, A. P. Chandrakasan, “Joint Algorithm-Architecture Optimization of CABAC,” Journal of Signal Processing Systems,  ICASSP-DISPS Track Special Issue, Vol. 69, Issue 3, pp. 239-252, May 2012. [ PDF ]
  • V. Sze, A. P. Chandrakasan, “A Highly Parallel and Scalable CABAC Decoder for Next-Generation Video Coding,” IEEE Journal of Solid-State Circuits (JSSC), ISSCC Special Issue, Vol. 47, No. 1, pp. 8-22, January 2012. [ PDF ]

2011

  • M. Budagavi, V. Sze, M. Zhou, “HEVC ALF decode complexity analysis and reduction,” IEEE International Conference on Image Processing (ICIP), pp. 745-748, September 2011. [ PDF ]
  • V. Sze, A. P. Chandrakasan, “Joint Algorithm-Architecture Optimization of CABAC to Increase Speed and Reduce Area Cost,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 1577–1580, May 2011. [ PDF ]
  • V. Sze, A. P. Chandrakasan, “A Highly Parallel and Scalable CABAC Decoder for Next-Generation Video Coding,” IEEE International Conference on Solid-State Circuits (ISSCC), pp. 126-127, February 2011. [ paper PDF | slides PDF ] Highlighted in EEtimes

2010

  • A. P. Chandrakasan, D. C. Daly, D. F. Finchelstein, J. Kwong, Y. K. Ramadass, M. E. Sinangil, V. Sze, N. Verma, “Technologies for Ultra Dynamic Voltage Scaling,” Proceedings of the IEEE, Vol. 98, No. 2, pp. 191-214, February 2010. [ PDF ]

2009

  • V. Sze, D. F. Finchelstein, M. E. Sinangil, A. P. Chandrakasan, “A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder,” IEEE Journal of Solid-State Circuits (JSSC), A-SSCC Special Issue , Vol. 44, No. 11, pp. 2943-2956, November 2009. [ PDF ]
  • D. F. Finchelstein, V. Sze, A. P. Chandrakasan, “Multi-Core Processing and Efficient On-Chip Caching for H.264 and Future Video Decoders,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), Vol. 19, No. 11, pp. 1704-1713, November 2009. [ PDF ] Nominated for Best Paper Award
  • V. Sze, A. P. Chandrakasan, “A High Throughput CABAC Algorithm Using Syntax Element Partitioning,” IEEE International Conference on Image Processing (ICIP), pp. 773-776, November 2009. [ paper PDF | slides PDF ]
  • A. P. Chandrakasan, F. S. Lee, D. D. Wentzloff, V. Sze, B. P. Ginsburg, P. P. Mercier, D. C. Daly, R. Blazquez, “Low-Power Impulse UWB Architectures and Circuits,” Proceedings of the IEEE, Vol. 97, No. 2, pp. 332-352, February 2009. [ PDF ]

2008

  • D. F. Finchelstein, V. Sze, M. E. Sinangil, Y. Koken, A. P. Chandrakasan, “A Low-Power 0.7-V H.264 720p Video Decoder,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 173-176, November 2008. [ paper PDF | slides PDF ] Student Design Contest Winner and selected as one of 9 noteworthy technical papers at the conference
  • V. Sze, M. Budagavi, A. P. Chandrakasan, M. Zhou, “Parallel CABAC for Low Power Video Coding,” IEEE International Conference on Image Processing (ICIP), pp. 2096-2099, October 2008. [ paper PDF | poster PDF ]

2007

  • V. Sze, A. P. Chandrakasan, “A 0.4-V UWB Baseband Processor,” IEEE International Symposium Low Power Electronics and Design (ISLPED), pp. 262-267, August 2007. [ paper PDF | slides PDF ] Finalist for Best Paper Award
  • B. P. Ginsburg, V. Sze, A. P. Chandrakasan, “A Parallel Energy Efficient 100Mbps Ultra-Wideband Radio Baseband,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), pp. 75-78, March 2007.

2006

  • V. Sze, R. Blazquez, M. Bhardwaj, A. Chandrakasan, “An Energy Efficient Sub-Threshold Baseband Processor Architecture for Pulsed Ultra-Wideband Communications,” IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. (III) 908-911, May 2006. [ paper PDF | slides PDF ]