Energy-Efficient
Multimedia Systems Group

Professor Vivienne Sze

Talks and Tutorials

MIT Professional Education Short Course on Designing Efficient Deep Learning Systems

Videos of talks and demos can be found on our YouTube channel.

  • V. Sze, “Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design,” UW-Madison Virtual Computer Architecture Seminar for Fall 2020, presented on September 29, 2020 [ Slides | Video ]
  • V. Sze, “Reducing the Carbon Emissions of ML Computing - Challenges and Opportunities,” Frontiers in Machine Learning 2020, presented on July 23, 2020 [ Slides | Video ]
  • V. Sze, “Efficient Computing For Low-Energy Robotics,” Purdue ECE Seminar, presented on July 16, 2020 [ Slides ]
  • V. Sze, “How to Evaluate Efficient Deep Neural Network Approaches,” Workshop on Efficient Deep Learning in Computer Vision at CVPR 2020, presented on June 15, 2020 [ Slides ]
  • V. Sze, “The Intersection of SSCS and AI — A Tale of Two Journeys,” SSCS and tinyML Webinar, presented on May 26, 2020 [ Slides | Video ]
  • V. Sze, “How to Evaluate Deep Neural Network Accelerators,” Workshop on On-Device Intelligence at MLSys 2020, presented on March 4, 2020 [ Slides | Video ]
  • V. Sze, “Efficient Computing for AI and Robotics,” MTL Seminar Series, presented on February 26, 2020 [ Slides ]
  • V. Sze, “How to Understand and Evaluate Deep Learning Processors,” International Solid-State Circuits Conference, presented on February 16, 2020 [ Slides ]
  • V. Sze, “Efficient Computing for Deep Learning, AI and Robotics,” Deep Learning Lecture Series, presented on January 15, 2020 [ Slides ]
  • V. Sze, “Co-Design Approaches for Efficient Deep Neural Networks: Challenges and Opportunities,” Workshop on Energy Efficient Machine Learning and Cognitive Computing at NeurIPS 2019, presented on December 13, 2019 [ Slides

  • V. Sze, “Efficient Processing of Deep Neural Networks: from Algorithms to Hardware Architectures,” Conference on Neural Information Processing Systems (NeurIPS), Invited Tutorial, presented on December 9, 2019 [ Slides | Video

  • V. Sze, T.-J. Yang, “Efficient Image Processing with Deep Neural Networks,” IEEE International Conference on Image Processing (ICIP), presented on September 22, 2019 [ Slides
  • V. Sze, “Domain-Specific Architectures for AI and Robotics: Opportunities and Challenges,” SIGARCH Visioning Workshop on Agile and Open Hardware for Next-Generation Computing at ISCA 2019, presented on June 23, 2019 [ Slides
  • V. Sze, “Balancing Efficiency and Flexibility for DNN Acceleration,” EMC^2: Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications
    • CVPR 2019 (June 16, 2019) [ Slides ]
    • ISCA 2019 (June 23, 2019) – with deep dive on Eyeriss v2 by Yu-Hsin Chen [ Slides ]
  • V. Sze, “Exploiting Redundancy for Efficient Processing of DNNs and Beyond,” Coding Theory for Large-Scale Machine Learning at ICML 2019, presented on June 15, 2019 [ Slides | Video

  • V. Sze, “Understanding the Challenges of Algorithm and Hardware Co-design for Deep Neural Networks,” Invited talk at Joint Workshop on On-Device Machine Learning & Compact Deep Neural Network Representations (ODML-CDNNR) at ICML 2019, presented on June 14, 2019 [ Slides | Video

  • V. Sze, “Energy-Efficient AI,” TEDxMIT, presented on May 28, 2019 [ Slides ]
  • V. Sze, “Efficient Computing for Robotics and AI,” ESE Spring Colloquia at University of Pennsylvania, presented on May 9, 2019 [ Slides
  • V. Sze, “Efficient Computing for AI and Robotics” [ Slides ] presented at
    • Xilinx Emerging Technology Symposium (April 11, 2019)
    • Stanford SystemX (April 11, 2019)
    • Berkeley Wireless Research Center (April 12, 2019)

  • V. Sze, “Efficient Computing for Autonomous Navigation of Miniaturized Robots,” MARS Conference 2019, presented on March 19, 2019 [ Slides ]
  • V. Sze, “Energy-Efficient AI,” MIT College of Computing Kickoff, presented on February 28, 2019 [ Slides ]
  • V. Sze, “Energy-Efficient Edge Computing for AI-driven Applications,” Distinguished Lecture at University of Toronto, presented on November 22, 2018 [ Slides ]
  • V. Sze, “Energy-Efficient Edge Computing for AI-driven Applications,” Keynote at 2018 International Conference on Field-Programmable Logic and Applications (FPL), presented on August 27, 2018 [ Slides ]
  • A. Suleiman, Z. Zhang, L. Carlone, S. Karaman, V. Sze, “Navion: An Energy-Efficient Visual-Inertial Odometry Accelerator for Micro Robotics and Beyond,” IEEE Hot Chips: A Symposium for High-Performance Chips, August 2018. [ Slides ] Highlighted in EETimes
  • V. Sze, “Energy-Efficient Processing at the Edge: From Compressing to Understanding Pixels,” Keynote at 2018 Picture Coding Symposium, presented on June 25, 2018 [ Slides ]
  • V. Sze, “Hardware for Machine Learning: Design Considerations,” Symposia on VLSI Technology and Circuits, Forum on Machine Learning Today and Tomorrow: Technology, Circuits and System View, presented on June 22, 2018 [ Slides ]
  • V. Sze, “Energy-Efficient Deep Learning: Challenges and Opportunities,” IEEE/SSCS IEEE Distinguished Lecture/Webinar, presented on April 10, 2018 [ Slides ]
  • V. Sze, “Understanding the Limitations of Existing Energy-Efficient Design Approaches for Deep Neural Networks,” Forum on The Next Waves of Machine and Deep Learning Hardware at CICC 2018, presented on April 9, 2018 [ Slides ]
  • V. Sze, “Energy-Efficient Edge Computing for AI-driven Applications,” Keynote at 2018 UIUC CSL Student Conference, presented on February 22, 2018 [ Slides ]
  • V. Sze, “Efficient Edge Solutions for Deep Learning Applications,” Short Course on Hardware Approaches to Machine Learning and Inference at ISSCC 2018, presented on February 15, 2018 [ Slides ]
  • V. Sze, “Efficient Processing for Deep Learning,” Embedded Vision Webinar, presented on September 28, 2017 [ Slides ]
  • “Tutorial on Hardware Architectures of Deep Neural Networks,” ISCA 2017, presented on June 24, 2017 (also appeared at MICRO-49) [ Website ]
    • Background of Deep Neural Networks [ slides ]
    • Survey of DNN Development Resources [ slides ]
    • Survey of DNN Hardware [ slides ]
    • DNN Accelerator Architectures [ slides ]
    • Advanced Technology Opportunities [ slides ]
    • Network and Hardware Co-Design [ slides ]
    • Benchmarking Metrics [ slides ]
    • Summary [ slides ]
    • References [ slides ]
    • Entire Tutorial [ slides ]
  • V. Sze, “What If Your Smart Phone Didn’t Need The Cloud?,” MIT ILP Europe Conference in Vienna, presented on March 29, 2017.
  • V. Sze, “Joint Design of Algorithms and Hardware for Energy-Efficient DNNs,” NIPS 2016 Workshop on Efficient Methods for Deep Neural Networks, presented on December 9, 2016. [ Slides ]
  • V. Sze, Y.H. Chen, “Building Energy-Efficient Accelerators for Deep Learning,” Deep Learning Summit Boston – RE•WORK, presented on May 12, 2017. [ Slides ]
  • V. Sze, “Energy-Efficient Hardware for Embedded Vision and Deep Convolutional Neural Networks,” [ Slides ] presented at
    • ICML 2016 Workshop on On-Device Intelligence (June 24, 2016)
    • CVPR 2016 Embedded Vision Workshop (July 1, 2016)
    • Embedded Vision Alliance (September 20, 2016)
    • ICCAD 2016 Workshop on Hardware and Algorithms for Learning On-a-chip (November 10, 2016)

  • V. Sze, M. Budagavi, “Design and Implementation of Next Generation Video Coding Systems (H.265/HEVC Tutorial),” IEEE International Symposium on Circuits and Systems (ISCAS), presented on June 1, 2014. [ Slides ]