Integrated Systems Group | Prof. Vladimir Stojanovic
Link: Home Link: News Link: About Link: Research Link: People Link: Publications Link: Teaching Link: Technology Link: Contact

Back to Main Research Page

Integrated CMOS Photonics

Energy-Efficient Monolithic CMOS Photonic NEtworks for manycore Processors


DARPA, NSF, FCRP IFC, Trusted Foundry, Intel, MIT CICS, NSERC, and Angstrom


Ben Moss, Michael Georgas, Jonathan Leu, Chen Sun. We collaborate with the groups of Prof. Rajeev Ram, Prof. Franz Kaertner, Prof. Judy Hoyt, Prof. Henry Smith and Prof. Erich Ippen at MIT , Prof. Krste Asanovic at UC Berkeley, and Prof. Milos Popovic at University of Colorado at Boulder.

This project is investigating the integration of photonics in SOI and bulk CMOS processes. The throughput bounds of traditional interconnect networks in microprocessors are being pushed to their limits. In past single-core processors, the number of long global wires constituted only a small fraction of the total. However, with the emergence of multi-core systems, where each core must communicate with each other as well as with off-chip memory, global interconnects have become a major bottleneck. The solution has been proposed through integrated photonic networks[1, 3], where multiple channels of information can be placed onto a single low-latency waveguide, reducing the number of interconnects and increasing the link bandwidth and efficiency. We are developing methods to integrate this exciting new technology from the transistor and circuit level through to the system architecture level.

Figure 1: The emergence of multi-core computing.

As an emerging technology, there are many cutting-edge research topics in integrated photonics, from device optimization to network architecture design. Our group focuses on the circuits and systems that interface with the optical devices, and we work closely with photonic device designers in an effort to co-design the devices and circuits for system-level optimization. We are actively investigating and implementing designs for optical modulators and receivers, optical clock distribution methods, and different network topologies based on integrated photonic link specifications [2].


Figure 2: System view of a 16-core integrated photonic on-chip network  

The photonics project has an aggressive tapeout schedule with multiple chips being sent for fabrication each year in processes such as IBM 45-nm SOI (the same process as the IBM Cell Processor in your PlayStation3). We are driven by implementation and testing our system and circuit models with measurement in silicon.

Figure 3: Optical-electrical link test station. The photo shows a link experiment being performed, where light is coupled from an optical fiber through the top of the chip. Electrical control is achieved through the PCB shown.




  1. Batten, C., A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic silicon photonics,” IEEE Symposium on High-Performance Interconnects, Stanford, CA, 10 pages, August 2008.
  2. Joshi, A., C. Batten, Y-J. Kwon, S. Beamer, K. Asanovic, and V. Stojanovic, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, CA, pp. 124-133, May 2009.
  3. Beamer, S., C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic and K. Asanovic, "Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics," ACM IEEE International Symposium on Computer Architecture, Saint-Malo, France, June 2010.
  4. Jason S. Orcutt, Anatol Khilo, Charles W. Holzwarth, Milos A. Popovic, Hanqing Li, Jie Sun, Thomas Bonifield, Randy Hollingsworth, Franz X. Kärtner, Henry I. Smith, Vladimir Stojanovic, and Rajeev J. Ram, "Nanophotonic integration in state-of-the-art CMOS foundries," Opt. Express 19, 2335-2346 (2011).
  5. M. Georgas, J.C. Leu, B. Moss, C. Sun, and V. Stojanovic, “Addressing Link-Level Design Tradeoffs for Integrated Photonic Interconnects,” [Invited] accepted for publication at IEEE Custom Integrated Circuits Conference, 8 pages, San Jose, CA, September 2011. (paper)
  6. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, “A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI,“ accepted for publication at European Solid-State Circuits Conference, Helsinki, Finland, 4 pages, September 2011. (paper)
  7. J.C. Leu and V. Stojanovic, “Injection-Locked Clock Receiver for Monolithic Optical Link in 45nm, “ accepted for publication at Asian Solid-State Circuits Conference, Jeju, Korea, 4 pages, November 2011.
  8. Georgas, M.; Orcutt, J.; Ram, R.J.; Stojanovic, V.; , "A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI," Solid-State Circuits, IEEE Journal of , vol.47, no.7, pp.1693-1702, July 2012.


  1. Georgas, Michael, “An Optical Data Receiver for Integrated Photonic Interconnects,” August 2009.
  2. Moss, Benjamin, “High-Speed Modulation of Resonant CMOS Photonic Modulators in Deep-Submicron Bulk-CMOS,” August 2009.
  3. Leu, Jonathan, "A 9GHz Injection Locked Loop Optical Clock Receiver in 32-nm CMOS," August 2010.

Technical Reports

  1. Beamer, S., C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic and K. Asanovic, “Re-architecting DRAM with Monolithically Integrated Silicon Photonics” (UC Berkeley EECS-2009-179).
Home / News / About / Research / People / Publications / Teaching / Technology / Contact © 2005 Massachusetts Institute of Technology
Link: Research Laboratory of Electronics at MIT Link: MIT
Link: Internal (Password Protected)