Journals and Magazines

1. O. Salehi-Abari, F. Lim, F. Chen, and Vladimir Stojanović, “Why Analog-to-Information Converters Suffer in High-Bandwidth Sparse Signal Applications,” to appear in IEEE Transactions on Circuits and Systems – I, 12 pages.(paper)
2. F. Lim and V. Stojanović, “On U-Statistics and Compressed Sensing II: Non-Asymptotic Worst-Case Analysis,” to appear in IEEE Transactions on Signal Processing, 26 pages.(paper)
3. F. Lim and V. Stojanović, “On U-Statistics and Compressed Sensing I: Non-Asymptotic Average-Case Analysis,” to appear in IEEE Transactions on Signal Processing, 34 pages.(paper)
4. F. Chen, F. Lim, O. Salehi-Abari, A. Chandrakasan, and V. Stojanović,” Energy Aware Design of Compressed Sensing Systems for Wireless Sensors under Performance and Reliability Constraints,“ IEEE Transactions on Circuits and Systems - I, vol.60, no.3, pp.650-661, March 2013.(paper)
5. Y. Li, Z. Li, O. Uyar, Y. Avniel, A. Megretski, and V. Stojanović, “High-throughput Signal Component Separator for Asymmetric Multi-level Outphasing Power Amplifiers” IEEE Journal of Solid-State Circuits, vol.48, no.2, pp.369-380, Feb. 2013.(paper)
6. M. Zhang, V. Stojanović and P. Ampadu, “Reliable Ultra-Low Voltage Cache Design for Many-Core Systems”, IEEE Transactions on Circuits and Systems – II: Express Briefs, vol.59, no.12, pp.858-862, Dec. 2012.(paper)
7. C. Batten, A. Joshi, V. Stojanovic and K. Asanovic, “Designing Chip-Level Nanophotonic Interconnection Networks [Invited],” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 137-153, June 2012.(paper)
8. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, "A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI [Invited]," IEEE Journal of Solid-State Circuits, vol. 47, no. 7, 10 pages, July 2012. (paper)
9. J.S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urosevic, M. Popovic, R. J. Ram and V. Stojanovic, “An Open Foundry Platform for High-Performance Electronic-Photonic Integration,” Optics Express, vol. 20, no. 11, pp. 12222-12232, May 2012 . (paper)
10. T.-J. K. Liu, D. Markovic, V. Stojanovic and E. Alon, "The Relay Reborn [Invited],” IEEE Spectrum, vol. 49, no. 4, pp. 40-43, April 2012. (paper)
11. J.S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanovic, and R. J. Ram, “Low-loss polysilicon waveguides fabricated in an emulated high-volume electronics process,” Optics Express, vol. 20, no. 7, pp. 7243–7254, March 2012. (paper)
12. F. Chen, A.P. Chandrakasan, and V. Stojanovic, “Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors,” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 744-756, March 2012. (paper)
13. R. Sredojevic and V. Stojanovic, “Fully-Digital Transmit Equalizer with Dynamic Impedance Modulation [Invited]”, IEEE of Journal Solid-State Circuits, vol. 46, no. 8, pp. 1857-1869 , August 2011. (paper)
14. S.D. Vamvakos, V. Stojanovic, and B. Nikolic, “Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis,” IEEE Transactions on Circuits and Systems-I, vol. 58, no. 6, pp. 1211-1224, June 2011. (paper)
15. S. Song and V. Stojanovic, “A 6.25 Gb/s Voltage-time Conversion Based Fractionally Spaced Linear Equalization Receiver for High-speed Links,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1183-1197, May 2011. (paper)
16. M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, D. Markovic, T.-J. King Liu, E. Alon, and V. Stojanovic, "Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications [Invited]," IEEE Journal of Solid-State Circuits, vol. 46, no. 1, pp. 308-320, Jan. 2011.(paper)
17. J.S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovic, H. Li, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanovic, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Optics Express, vol. 19, no. 3, pp. 2335-2346, January 2011.(paper)
18. H. Kam, T.-J. K. Liu, V. Stojanovic, D. Markovic, and E. Alon, “Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic,” IEEE Transactions on Electron Devices, vol. 58, no. 1, pp. 236-250, January 2011.(paper)
19. B. Kim and V. Stojanovic, “An Energy-Efficient Equalized Transceiver for RC-Dominant Channels,” IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1186-1197, June 2010.(paper)
20. B. Bond, Z. Mahmood, R. Sredojevic, Y. Li, A. Megretski, V. Stojanovic, Y. Avniel, and L. Daniel, “Compact Modeling of Nonlinear Analog Circuits using System Identification via Semi-Definite Programming and Robustness Certification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 1149-1162, Aug. 2010.(paper)
21. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic CMOS silicon photonics [Invited],” IEEE Micro, vol. 29, no. 4, pp. 8-21, 2009. (paper)
22. N. Blitvic, M. Lee, and V. Stojanovic, “Channel Coding for High-speed Links: A systematic look at code performance and system simulation [Invited],” IEEE Transactions on Advanced Packaging, vol. 2, no. 32, pp. 268-279, 2009. (paper)
23. B. Kim and V. Stojanovic, “Modeling and design framework: Equalized and repeated interconnects for networks-on-chip [Invited],” IEEE Design & Test of Computers, vol. 25, no. 5, pp. 430-439, 2008. (paper)
24. T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kärtner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, “Silicon photonics for compact, energy-efficient interconnects [Invited],” Journal of Optical Networking, vol. 6, no. 1, pp. 63-73, 2007. (paper)

Conferences

1. B.R. Moss, C. Sun, M. Georgas, J. Shainline, J. S Orcutt, J. C. Leu, M. Wade, H. Li, R. Ram, M. A. Popović, and V. Stojanović, “A 1.23 pJ/bit 2.5Gb/s Monolithically-Integrated Optical Carrier-Injection Ring Modulator and All-Digital Driver Circuit in Commercial 45nm SOI,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 126-127, February 2013.(paper)(talk)
2. J.S. Orcutt, R. Ram, and V. Stojanović, “Integration of Silicon Photonics into Electronic Processes,” SPIE Photonics West, 8 pages, February 2013.(talk)
3. F. Lim, and V. Stojanovic “Non-Asymptotic Analysis of Compressed Sensing Random Matrices : An U-Statistics Approach,” IEEE International Conference on Communication, Ottawa, Canada, pp. 2511-2515, June 2012.(paper)
4. J.S. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, H. Li, J. Sun, M. Weaver, E. Zgraggen, M. Popovic, R. J. Ram and V. Stojanovic, "Low Loss Waveguide Integration within a Thin-SOI CMOS Foundry," IEEE Optical Interconnects Conference, Santa Fe, NM, 2 pages, May 2012.(paper)(talk)
5. G. Kurian, C. Sun, O. Chen, J. Miller, L. Wei, J. Michel, D. Antoniadis, L-S. Peh, L. C. Kimerling, V. Stojanovic and A. Agarwal, "Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System using Real Application Workloads," 26th IEEE International Parallel & Distributed Processing Symposium, Shanghai, China, 12 pages, May 2012.(paper)(talk)
6. C. Sun, O. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh, and V. Stojanovic, "DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling," 6th ACM/IEEE International Symposium on Networks-on-Chip, Lyngby, Denmark, 26 pages, May 2012.(paper)(talk)
7. E. Timurdogan, E., A. Biberman, D. Trotter, C. Sun, M. Moresco, V. Stojanovic, M. Watts, "Automated Wavelength Recovery for Microring Resonators," Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2012.(paper)
8. O. Salehi-Abari, F. Chen, F. Lim, and V. Stojanovic, "Performance Trade-offs and Design Limitations of Analog-to-Information Converter Front-Ends," IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, 4 pages, March 2012. (paper)(talk)
9. J.C. Leu and V. Stojanovic," Injection-Locked Clock Receiver for Monolithic Optical Link in 45nm," Asian Solid-State Circuits Conference, Jeju, Korea, pp. 149-152, November 2011.         (paper)(talk)
10. H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, T-J. K. Liu, and V. Stojanovic," Design and Demonstration of Micro-Electro-Mechanical Relay Multipliers," Asian Solid-State Circuits Conference, Jeju, Korea, pp. 117-120, November 2011. (paper)(talk)
11. M. Georgas, J.C. Leu, B. Moss, C. Sun, and V. Stojanovic, “Addressing Link-Level Design Tradeoffs for Integrated Photonic Interconnects,” [Invited] IEEE Custom Integrated Circuits Conference, 8 pages, San Jose, CA, September 2011.(paper)(talk)
12. M. Georgas, J. Orcutt, R. J. Ram, and V. Stojanovic, “A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI," European Solid-State Circuits Conference, Helsinki, Finland, pp. 407-410, September 2011.(paper)(talk)
13. J. S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanovic, and R. J. Ram, “Low-Loss Polysilicon Waveguides Suitable for Integration within a High-Volume Electronics Process,” Optical Society of America - CLEO/QELS Conference, Baltimore, MD, 2 pages, May 2011.(paper)
14. F. Chen, A. Chandrakasan, and V. Stojanovic, "A Signal-agnostic Compressed Sensing Acquisition System for Wireless and Implantable Sensors," IEEE Custom Integrated Circuits Conference, September, 2010. (paper)
15. F. Chen, A. Chandrakasan, and V. Stojanovic, "A Low-power Area-efficient Switching Scheme for Charge-sharing DACs in SAR ADCs," IEEE Custom Integrated Circuits Conference, September, 2010.(paper)
16. H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T.-J. King Liu, E. Alon, V. Stojanovic, and D. Markovic, "Analysis and Demonstration of MEM-Relay Power Gating," IEEE Custom Integrated Circuits Conference, September, 2010.(paper)
17. R. Sredojevic and V. Stojanovic, “Digital Link Pre-emphasis with Dynamic Driver Impedance Modulation”, IEEE Custom Integrated Circuits Conference, San Jose, CA, September 2010.(paper)(talk)
18. S. Beamer, C. Sun, Y-J. Kwon, A. Joshi, C. Batten, V. Stojanovic, and K. Asanovic, ”Re-architecting DRAM with Monolithically Integrated Silicon Photonics,” 37th International Symposium on Computer Architecture (ISCA-37), Saint-Malo, France, pp. 129-140, June 2010. (paper)(talk)
19. V. Stojanovic, A. Joshi, C. Batten, Y-J. Kwon, S. Beamer, C. Sun, and K. Asanovic, “Design-space Exploration for CMOS Photonic Processor Networks,” [Invited] Optical Fiber Communication Conference, San Diego, CA, pp. 1-3, March 2010.(paper)(talk)
20. F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.-J. King Liu, D. Markovic, V. Stojanovic, and E. Alon, "Demonstration of Integrated Mico-Electro-Mechanical (MEM) Switch Circuits for VLSI Applications," IEEE International Solid-State Circuits Conference, pp. 150-151, February 2010. (paper)(talk) (Winner of the 2010 Jack Raper Award for Outstanding Technology Directions Paper)
21. J.S. Orcutt, A. Khilo, M. A. Popovic, C. W. Holzwarth, H. Li, J. Sun, B. Moss, M. S. Dahlem, E. P. Ippen, J. L. Hoyt, V. Stojanovic, F. X. Kartner, H. I. Smith, R. J. Ram, “Photonic integration in a commercial scaled bulk-CMOS process,” IEEE International Conference on Photonics in Switching, Pisa, Italy, pp. 1-2, September 2009. (paper)
22. F. Chen, A. Chandrakasan, and V. Stojanovic, "An Oscilloscope Array for High-Impedance Device Characterization," IEEE European Solid-State Circuits Conference, Athens, Greece, September 14-18, 2009. (paper)(talk)
23. A. Joshi, B. Kim, and V. Stojanovic,”Designing Energy-efficient Low-diameter On-chip Networks with Equalized Interconnects,” IEEE Symposium on High-Performance Interconnects, New York, NY, 10 pages, August 2009.(paper)(talk)
24. Y. Li and V. Stojanovic, "Yield-driven Iterative Robust Circuit Optimization Algorithm," ACM/IEEE Design Automation Conference, San Francisco, CA, 6 pages, July 2009.(paper)(talk)
25. S. Song, B. Kim, and V. Stojanovic, "A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion," IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 222-223, June 2009. (paper)(talk)
26. V. Stojanovic, A. Joshi, C. Batten, Y-J. Kwon, K. Asanovic, “Manycore Processor Networks with Monolithic Integrated CMOS Photonics,” Optical Society of America - CLEO/QELS Conference [Invited], Baltimore, MD, 2 pages, June 2009.(paper)(talk)
27. S. Beamer, K. Asanovic, C. Batten, A. Joshi, and V. Stojanovic, “Designing multi-socket systems using silicon photonics,” in Proceedings of the 23rd International Conference on Supercomputing, Yorktown Heights, NY, pp. 521-522, June 2009.
    (paper)
28. A. Joshi, C. Batten, Y-J. Kwon, S. Beamer, K. Asanovic, and V. Stojanovic, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, CA, pp. 124-133, May 2009.
    (paper)(talk)
29. B. Kim and V. Stojanovic, "A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmitter Filter and Transimpedance Receiver in 90nm CMOS Technology,"IEEE International Solid-State Circuit Conference, February 2009.
    (paper)(talk)
30. R. Sredojevic and V. Stojanovic, “Optimization-based Framework for Simultaneous Circuit and System Design-Space Exploration: A High-Speed Link Example,” IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 314-321, November 2008. (paper)(talk) (Winner of 2008 IEEE/ACM William J. McCalla Best Paper Award)
31. F. Chen, H. Kam, D. Markovic, T.J. King, V. Stojanovic, and E. Alon, “Integrated Circuit Design with NEM Relays,” IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, 8 pages, November 2008. (paper)(talk)
32. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic silicon photonics,” to appear in IEEE Symposium on High-Performance Interconnects, Stanford, CA, 10 pages, August 2008. (paper)(talk)
33. N. Blitvic, L. Zheng, and V. Stojanovic ,”Low-complexity Pattern-eliminating Codes for ISI-limited Channels,” IEEE International Communications Conference, Beijing, China, 7 pages, pp. 1214-1219, May 2008. (paper)(talk)
34. C. W. Holzwarth, J. S. Orcutt, H. Li, M. A. Popovic, V. Stojanovic, J. L. Hoyt, R. J. Ram, and H. I. Smith, “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
35. J.S. Orcutt, A. Khilo, M. A. Popovic, C. W. Holzwarth, B. Moss, H. Li, M. S. Dahlem, T. D. Bonifield, F. X. Kärtner, E. P. Ippen, J. L. Hoyt, R. J. Ram, and V. Stojanovic, “Demonstration of an Electronic Photonic Integrated Circuit in a Commercial Scaled Bulk CMOS Process,” Optical Society of America - CLEO/QELS Conference, San Jose, CA, 2 pages, May 2008. (paper)(talk)
36. B. Kim and V. Stojanovic, “Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework,” IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, pp. 552-559, November 2007.    (paper)(talk)
37. F. Chen, A. Joshi, V.Stojanovic, and A. Chandrakasan, “Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications,” ACM International Conference on Nano-Networks, Catania, Italy, p.8, September 2007.    (paper)(talk)
38. N. Blitvic and V. Stojanovic, “Statistical Simulator for Block Coded Channels with Long Residual Interference,” IEEE International Conference on Communications, Glasgow, Scotland, pp. 6287-6294, June 2007. (paper)(talk)

Theses

Ph.D. Theses

1. Chen, Fred, "Energy-Efficient Wireless Sensors: Fewer Bits, Moore MEMS," September 2011. (thesis)(talk)
2. Song, Sanquan, “Fractionally Spaced Equalization for High-Speed Links,” January 2011. (thesis)(talk)
3. Kim, Byungsub, “Equalized On-Chip Interconnect: Modeling, Analysis, and Design,” January 2010.
   (thesis)(talk) (Honorable Mention of the Jin-Au Kong Award for best Electrical Engineering PhD Thesis)

Engineer Theses

1. An, Wei, "Complete VLSI Implementation of Improved Low Complexity Chase Reed-Solomon Decoders,” September 2010. (thesis)

M.S. Theses

1. Salehi-Abari, Omid, “Building Compressed Sensing Systems: Sensors and Analog-to-Information Converters,” August 2012.(thesis)
2. Chen, Sun, “Design Space Exploration of Photonic Interconnects,” August 2011. (Ernst A. Guillemin Master's Thesis Award -2nd place)(thesis)
3. Uyar, Oguzhan, “Front-end Circuits for a Photonic Analog-to-Digital Converter,” August 2011.(thesis)
4. Leu, Jonathan, "A 9GHz Injection Locked Loop Optical Clock Receiver in 32-nm CMOS," August 2010. (thesis)
5. Georgas, Michael, “An Optical Data Receiver for Integrated Photonic Interconnects,” August 2009. (thesis)
6. Moss, Benjamin, “High-Speed Modulation of Resonant CMOS Photonic Modulators in Deep-Submicron Bulk-CMOS,” August 2009. (thesis)
7. Shamim, Imran “Energy Efficient Links and Routers for Multi-Processor Computer Systems,” August 2009.(thesis)
8. Sredojevic, Ranko, “Bridging the gap: An Optimization-based Framework for Fast, Simultaneous Circuit and System Design Space Exploration,” January 2008. (thesis)
9. Blitvic, Natasa, “Channel Coding for High-Speed Links,” November 2007. (Ernst A. Guillemin Master's Thesis Award -2nd place)(thesis)

M.Eng. Theses

1. Warnakulasuriyarachchi, Dilini, “Design and Simulation of a PCI Express Gen3.0 Communication Channel,” May 2010.
2. Wu, Henry, “System Architecture for a Mode-Matched MEMS Gyroscope,” May 2009. (thesis)
3. Ma, Yunjie, “Companding Techniques for High Dynamic Range Audio CODEC Receiver Path,” May 2009. (thesis)
4. Price, Michael, “Asynchronous Data-dependent Jitter Compensation,” February 2009. (thesis) (Francis Reintjes VI-A Thesis Award, David Adler Memorial Master's of Engineering Thesis Award in Electrical Engineering)
5. Kalantarian, Asad, “Package and PCB Solutions for High-Speed Data Link Applications,” August 2008.
   (thesis)
6. Clough, Andrew L., “Increasing Adder Efficiency by Exploiting Input Statistics,” May 2007.(thesis)
7. Moore, Alexander W., “On-Die Signal Integrity Monitoring of Gigabit Serial I/Os,” September 2006.
   (thesis)
8. Lee, Maxine, “Channel-and-Circuits Aware, Energy-Efficient Coding for High Speed Links,” September 2006.(thesis)

Technical Reports