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Sponsors

NEC Research Fund, IBM Faculty Award, Intel, IFC, Semicondcutor Research Corporation Program, CICS, Trusted Foundry Program

People

Byungsub Kim and Professor Vladimir Stojanovic

In recent high performance processor design, cross-hierarchical optimization of on-chip networks and overall chip architecture improves the performance-power efficiency significantly [1]. Though equalized on-chip interconnects have been proposed to improve the network efficiency [2, 3], the cross-hierarchical optimization of equalized interconnects have been a difficult problem due to design complexity.

The first effort of this project focused on a modeling and tool framework for fast design space exploration of equalized on-chip interconnects by exporting abstracted low level design parameters to a link model [4]. Using this tool, we can explore how the transistor and wire parameters affect link performance, equalization coefficients and architecture-friendly metrics like delay, power, and throughput density. With this approach, we are able to find the best link design for target throughput, power and area constraints, thus enabling the architectural optimization of energy-efficient on-chip networks. Figure 1 shows optimization results comparing interconnect metrics between the LCM [5] and the repeated interconnects using our tool. Our simulation shows that the equalized LCM interconnect is much more power efficient than the repeated interconnect for given target throughput density [4].

In second phase, we demonstrated two circuit techniques which enhance the power efficiency of eqaulized interconnect: charge-injecting (CI) non-linar transmitter and trans-impedance amplifier (TIA) receiver. Two test chips are taped out in 90nm CMOS technology and figure 2 shows the measured eye result [6] from the first chip.

Figure 1: Interconnects data rate density and power efficiency trade-off		Figure 2:Measured eye opening over 10mm equalized differentia interconnect.

References

1. Kumar, R.; Zyuban, V.; Tullsen, D. M., “Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling,” in Proc. 32nd International Symposium on Computer Architecture, 2005.

2. A.P. Jose, G. Patounakis and K.L. Shepard "Near speed-of-light on-chip interconnects using pulsed current-mode signalling," VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on no. SN -, pp. 108-111, 2005.

3. Schinkel, D., Mensink, E., Klumperink, E.A., Tuijl, E. van and Nauta, B. "A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects," Solid-State Circuits, IEEE Journal of vol. 41, no. 1 SN - 0018-9200, pp. 297-306, 2006.

4. B. Kim and V. Stojanovic, "Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework," ICCAD 2007.
5. H. Hatamkhani, K.J. Wong, R. Drost and C.K. Yang "A 10-mW 3.6-Gbps I/O transmitter," VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on no. SN -, pp. 97-98, 2003.
6. B. Kim and V. Stojanovic, "A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmitter Filter and Transimpedance Receiver in 90nm CMOS Technology," IEEE ISSCC, Feb. 2009.