Prof. Karl K. Berggren and Dr. P. Donald Keathley
Alessandro Buzzi wins “Best Presentation” at WOLTE15
Alessandro Buzzi won the award for Best Presentation at WOLTE15 for his presentation entitled “Building blocks design for superconducting nanowire asynchronous logic” which took place on June 8, 2022.
Superconducting nanowires have emerged in recent years as a candidate for low-power electronics . In particular, their inherent spiking behavior  and the possibility of integration with superconducting loop memory cells  make them an excellent candidate for asynchronous spiking computing. Although some proof-of-concept devices have been demonstrated, the lack of reliable standard cells that combine memory and logic functions has hindered the design of larger circuits.
We present an approach for digital logic based on niobium nitride superconducting nanowires, in which the information is stored in a superconducting loop and altered asynchronously by the inputs.
Additionally, we show how building blocks are designed and combined to reproduce circuits equivalent to lookup tables, flip-flops, shift registers, and linear feedback shift registers.
Fig.1 displays a destructive readout memory, our elementary building block. This device consists of a superconducting loop with two parallel branches. The constant bias current is transferred between the branches using two nanocryotrons (nTron), three-terminal components able to modulate the
switching current of a superconducting channel from a gate input . This basic design allows for further functionalities by slight modifications of the structure. For example, another input on the left side can be added to obtain an OR gate, moving the inputs on the right branch will produce a NOR gate while the combination of multiple loops can be used to make sequential elements and circuits.
We simulated the above-mentioned circuits with SPICE and verified their behavioral and electrical characteristics. Moreover, we experimentally demonstrated the correct function of the destructive readout memory (Fig. 1). We plan to fabricate and characterize the single-loop gates and integrate them into multi-block structures. Our work paves the way for the realization of asynchronous superconducting logic. We aim to develop a reliable system of standard cells that would provide a basis for future integrations of ultra-low-power circuits.